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IC16F 2N3645 Q150ST AH844 IS45S 68HC05E1 91F467BA NC7WV17
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  1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2006, zarlink semiconductor inc. all rights reserved. features ? 12 10/100 mbps autosensing, fast ethernet ports with reduced mii interface ? 32-bit wide bi-directional pipe at 100 mhz provides 6.4 gbps pipe to connect two mds212 chips ? supports up to 3.572 mpps system throughput using non-blocking architecture ? high performance layer 2 packet forwarding and filtering at full wire speed. ? very low latency through single store and forward at ingress port and cut-through switching at destination ports ? port trunking and load sharing for high bandwidth links between switches ? on-chip address lookup engine and memory for up to 2 k mac addresses ? up to 64 k using management cpu memory ? supports up to 4 k mac addresses with 24 ports (2-chip solution) ? up to 16 k using external buffer memory ? parallel flash interface for fast self initialization ? supports packet filtering and port security ? system wide filtering ? static mac destination and source address filtering ? vlan for multicast/broadcast filtering ? protocol filtering ? local port filtering ? aging control for secure mac addresses ? provides 256-port and id tagged virtual lans (vlans) 802.1q ? id tagging insertion/extraction ? supports ip mu lticasting through igmp snooping ? xpressflow quality of service (qos), ieee 802.1p, supports 4 level transmission priorities, weighted fair queuing based packet scheduling, user mapping of priority levels and weights ? full duplex ethernet ieee 803.2x flow control minimizes traffic congestion ? supports back-pressure flow control for half duplex mode ? flooding and broadcasting control ? link status and tx/rx activity through serial led interface ? standard software modules available: ? browser, gui, a nd text menu ? ieee 802.1d spanning tree algorithm ? snmp management ? telnet for remote control console ? automatic booting via tftp protocols. ? remote monitoring (rmon) and storage for a management agent ? igmp for ip multicast ? gvrp, gmrp ? packaged in 456-pin ball grid array april 2006 ordering information mds212cg 456 pin hsbga trays MDS212CG2 456 pin hsbga** trays **pb free tin/silver/copper 0 c to 70 c mds212 12-port 10/100mbps ethernet switch data sheet figure 1 - 24 10/100mbps port system configuration sdram cpu flash sram sram mds212 cpu bus 64 bit 64 bit 12 xpipe 32 bit mds212 12 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet 4 x 10/100 fast ethernet
mds212 data sheet 2 zarlink semiconductor inc. description the mds212 is a 12-port 10/100 mbps high-performance, non-blocking ethernet switch with on-chip address memory and address lookup engine. a single chip provi des 12 - 10/100 mbps ports. the mds212 can be utilized in both managed and unmanaged switching applications. the 3.2 gbps xpipe allows a high-speed connection between two mds212 chips, providing a optimal, low-cost, workgroup witch with 24 10/10 0 fast ethernet ports. in half-duplex mode, all ports support back pressure flow cont rol to minimize the risk of losing data for long activity bursts. in full-duplex mode, ieee 802.3x frame based fl ow control is used. with full -duplex capabilities, the fast ethernet ports supports 200 mbps aggregate bandwidth connections. the mds212 supports port trunking/load sharing on the 10/100 mbps ports. port trunking/load sharing can be used to group ports between inter linked switches for increased system bandwidth. ports within a trunk must reside within a single mds212, such that trunks may not be confi gured across two switches. the on-chip address lookup en gine supports up to 2 k mac addresses and up to 256 ieee 802.1q virtual lans (vlan). each port may be programmed to recognize vlans, and will transmit frames along with their vlan tags, for interoperability, to system s that support vlan tagging. each port independently collects statistical information using snmp and the remote monitoring management information base (rmon ? mib). access to these statistical counter/registers are provided via the cpu interface. snmp management frames may be received and/or transmit ted via the cpu interface and thus creates a complete network management solution. the mds212 utilizes cost effective, high performance, pipelined sbram to achieve full wire speed on all ports simultaneously. data is buffered into memory, using 0-128 byte bursts, from the ingress ports, and transferred to an internal transmit fifo, before being sent from the fr ame memory to the egress output ports. extremely high memory bandwidth is therefore achieved, which allows eac h of the ports to be active without creating a memory bottleneck. the mds212 is fabricated with 2.5 v te chnology, where the inputs are 3.3 v to lerant and the outputs are capable of directly interfacing to low-voltage ttl levels. the mds212 is packaged in a 456-pin ball grid array.
mds212 data sheet 3 zarlink semiconductor inc. figure 2 - system block diagram note: all registers are 32-bit width. the control bus is 32-bits wide and the memory bus is 64-bits wide. the mds212 contains 12 fast ethernet ports. the led interface has 3 output signals (1 data and 2 control). the xpipe is 32-bits wide. cpu interface registers hisc tm switch control memory 2k sram search engine frame memory interface frame buffer memory frame engine twelve 10/100macs reduced xpipe engine rmii led xface 64 32 32 32 64 64 64 64 64 64 32 64 64 3.2gbps xpressflow tm pipe 32 sbram
mds212 data sheet table of contents 4 zarlink semiconductor inc. 1.0 ball-signal description and assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 ball-signal assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 ball-signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 the media access control (mac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 mac configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 the inter-frame gap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 ethernet frame limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 collission handling and avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 vlan support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 mac control frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 collision-based flow control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9.1 ieee 802.3x flow cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.0 frame engine description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 transmission scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0 frame buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 frame buffer memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 frame buffer memory usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 memory allocation of a managed system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.2.1.1 frame data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.1.2 transmission queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.1.3 mailing list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.1.4 vlan table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.1.5 vlan mac association table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.2 unmanaged system memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 the frame memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 layer 2 search process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 vlan unaware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 vlan aware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 address and vlan learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 flooding and packet control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6 ip multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.0 the high density instruction set computer (hisc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 hisc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3 hisc operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.3.1 resource initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.2 resource management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.3 switching database management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.4 send and receive frames for management cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 communication between hisc and switching hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 7.4.1 communication between search engine and hisc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.2 communication between hisc and frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5 communication between management cpu and hisc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5.1 cpu-hisc communication using queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
mds212 data sheet table of contents 5 zarlink semiconductor inc. 7.5.2 mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5.2.1 cpu-hisc mail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5.2.2 hisc-cpu mail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.0 the xpipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 xpipe connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2 xpipe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.0 physical layer (phy) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 reduced mii (rmii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.0 the control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 external cpu support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1.1 power on/reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1.2 cpu bus clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1.3 address and data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.4 bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.5 input/output mapped interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1.6 interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 control bus cycle waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 the cpu interface in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3.1 arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4 cpu interface in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4.1 cpu access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.0 the led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1.1 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.1.2 port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1.3 led interface time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.0 data forwarding protocol and data fl ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.1 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.1.1 frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.1.2 unicast frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.1.3 multicast frame forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 flow for data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2.1 unicast data frame to lo cal device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2.2 unicast data frame to re mote device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2.3 multicast data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3 flow for cpu control frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3.1 cpu transmitting unicast cpu frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3.2 cpu transmitting multicast cpu frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3.3 cpu receiving unicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3.4 cpu receiving multicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.0 port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1.1 physical pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1.2 setting register for port mirrorin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1.2.1 apmr- port mirroring register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14.0 virtual local area networks (vlan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2 vlan implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2.1 static definitions of vlan member ship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2.2 dynamic learning of vlan membersh ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 14.2.3 dynamic learning of remo te vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
mds212 data sheet table of contents 6 zarlink semiconductor inc. 14.2.4 mds212 data stru ctures for vlan implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.4.1 vlan id table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2.4.2 vlan mac table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.2.4.3 vlan port mapping tabl e (vmap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.2.5 port vlan id (pvid) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.0 ip multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.2 igmp and ip multicast filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.3 implementation in mds212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.3.1 mct table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3.1.1 mct structure for unicast frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3.2 mct structure for ip multicast packe t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.0 quality of service (qos). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.1 weighted round robin transmission strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.2 buffer management functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.1 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.1 select one forwarding port per tr unk group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17.2.2 blocking multicast packets back to the source trunk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.3 mac address assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.0 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1 device configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.1 gcr - global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.2 dcr0 - device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2.1.3 dcr1 - signature, revision & id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.2.1.4 dcr2 - device configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 18.2.1.5 dcr3 - interfaces status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 18.2.1.6 memp - memory packed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18.2.2 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.2.3 buffer memory interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.1 mwars - memory write address register - single cycle . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.2.3.2 mrars - memory read address register - single cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18.2.3.3 address registers for burst cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 18.2.3.4 memory read/write data register s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 18.2.3.5 vtb - vlan id table ba se pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.2.3.6 mbcr - multicast buffer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.7 rama - ram counter block access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.2.3.8 reserve register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.3.9 reserve register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4 frame control buffers management register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.1 fcbsl - fcb queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.2 fcbst - fcb queue - buffer low threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2.4.3 bct - (fcb) buffer counter threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.4.4 bchl - buffer counter hi-low select ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 18.2.5 queue management register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.1 cinq - cpu input queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.2.5.2 cotq - cpu output queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 18.2.6 switching control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.1 hpcr - hisc processor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
mds212 data sheet table of contents 7 zarlink semiconductor inc. 18.2.6.2 hmcl0 - hisc micro-code loadin g port ? low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18.2.6.3 hmcl1 - hisc micro-code loading port ? high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.2.6.4 ms0r micro sequence 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 18.2.6.5 ms1r micro sequence 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 18.2.6.6 flooding control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.7 mcat - mct aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.8 tpmxr - trunk port mapping table index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.2.6.9 tpmtd - trunking port mapping table data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.6.10 ptr - pacing time regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 18.2.6.11 mtcr - mct threshold & counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.7 link list management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.7.1 lks - link list status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 18.2.7.2 ambx - mail box access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.7.3 afml - free mail box list access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 18.2.8 access control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.8.1 avtc - vlan type code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2.8.2 axsc - transmi ssion scheduling control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.8.3 attl - transmission timing cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.9 mii serial management c hannel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 18.2.9.1 amiic - mii command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 18.2.9.2 amiis - mii status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.2.10 flow control management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.1 afcria - flow control ram input address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.2 afcrid0 - flow control ram input data 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.3 afcrid1 - flow control ram input data 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.4 afcr - flow control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18.2.10.5 amar[1:0] - multicast address reg. for mac co ntrol frames. . . . . . . . . . . . . . . . . . . . . 88 18.2.10.6 amct - mac control frame type code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.7 adar [1:0] - base mac address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 18.2.10.8 adaor0 - mac offset address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.9 adaor1 - mac offset address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 18.2.10.10 acktm - timer for sof checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.11 afcht10 - flow control hold time of 10mbps po rt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.12 afcht 100 - flow control hold time of 100mbps port . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.13 afcoft10 - flow control off time of 10mbps po rt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.2.10.14 afcoft100 - flow control off time of 100mbps port. . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.11 access control function group 2 (chip level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 18.2.11.1 apmr - port mirroring register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.11.2 pfr - protocol filtering register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18.2.11.3 thkm [0:7] - trunking forwarding port mask 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 18.2.11.4 ipmcas - ip multicast mac address signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.5 ipmcmsk - ip multicast mac address mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.6 cfcbhdl - fcb handle register for cpu read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 18.2.11.7 cpu access internal rams (tables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 18.2.11.8 cpuircmd - cpu internal ram command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 18.2.11.9 cpuirdat - cpu internal ram da ta register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18.2.11.10 cpuirrdy - internal ram read ready for cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18.2.11.11 ledr - led register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18.2.12 ethernet mac port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18.2.12.1 ecr0 - mac port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 18.2.12.2 ecr1 - mac port configuration r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 18.2.12.3 ecr2 - mac port inte rrupt mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
mds212 data sheet table of contents 8 zarlink semiconductor inc. 18.2.12.4 ecr3 - mac port inte rrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 18.2.12.5 ecr4 - port status counter wrapped signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18.2.12.6 pvid register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 20.0 ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 20.1 xpipe interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 20.3 local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
mds212 data sheet list of figures 9 zarlink semiconductor inc. figure 1 - 24 10/100mbps port system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 - frame buffer memory configurat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4 - memory map of managed system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5 - memory map of an unmanaged system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 6 - typical packet header information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7 - xpipe system block diagram for the mds212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8 - xpipe message header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 9 - basic timing diagram of xpipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10 - cpu interface configuration in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11 - control bus configuration in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12 - control bus i/o and flash bus access operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13 - block diagram of the arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 14 - an example of byte swapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15 - led interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16 - time diagram of led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17 - configuration of mi rror port for mds212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18 - data structure diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 19 - vlan id table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 20 - vlan mac table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 21 - port mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 22 - forwarding port mask table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 23 - multicast packet forwarding exam ple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 24 - xpipe interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 25 - cpu bus interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 26 - cpu bus interface - input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 27 - local memory interface - input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 28 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 29 - port mirroring interface - input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 30 - port mirroring interface - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 31 - reduce media independent interface - input setup an d hold timing . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 32 - reduce media independent interface - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 figure 33 - led interface - output delay ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
mds212 data sheet list of tables 10 zarlink semiconductor inc. table 1 - type and size of memory chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 2 - frame buffer memory usage for managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3 - frame buffer memory usage for unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4 - summary description of the source and target end sig nals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5 - rmii specification signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6 - bootstrapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7 - little and big endian byte swapping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8 - led signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9 - mds212 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 10 - global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 11 - device status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 12 - hpcr - hisc processor control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 13 - amiis - mii status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 14 - ac characteristics - xpipe interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 15 - ac characteristics - cpu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 16 - ac characteristics - local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 17 - ac characteristics - port mirro ring interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 18 - ac characteristics - reduced media independent interf ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 19 - ac characteristics - led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
mds212 data sheet 11 zarlink semiconductor inc. 1.0 ball-signal d escription and assignments vcc = 3.3 vdc for i/o 16 (balls) vdd = 2.5 vdc for core logic (10 balls) gnd = digital ground for both vcc and vdd (42 balls) avdd = 2.5 vdc for analog pll (1 ball) agnd = isolated analog ground for avdd (1 ball) nc = no connection reserved = do not connect 1 234567891011121314151617181920212223242526 aagndl_a2 0 l_a1 9 l_a1 1 l_a8 l_a4 x_d o29 x_d o25 x_d o20 x_d o16 x_d o13 x_d o8 x_d o5 x_d o2 x_dc lko x_di 29 x_di 25 x_di 21 x_di 17 x_di 12 x_di 8 x_di 4 x_di 2 p_cs i# p_re q1 p_gn tc b reser ved rese rved l_a1 8 l_a1 4 l_a1 0 l_a5 x_d o30 x_d o26 x_d o21 x_d o18 x_d o14 x_d o10 x_d o4 x_d o3 x_fc o x_di 28 x_di 23 x_di 20 x_di 16 x_di 11 x_di 7 x_di 3 x_dc lki rese rved nc nc cavddrese rved rese rved l_a1 7 l_a1 3 l_a6 x_d o31 x_d o28 x_d o24 x_d o19 x_d o15 x_d o12 x_d o6 x_d o1 x_di 31 x_di 27 x_di 22 x_di 18 x_di 14 x_di 10 x_di 6 x_dn i rese rved p_re qc p_br dy# p_bl ast d l_d4 l_d1 l_cl k nc l_a1 6 l_a1 2 l_a7 l_a3 x_d o27 x_d o23 x_d o17 x_d o11 x_d o7 x_de no x_di 30 x_di 24 x_di 19 x_di 15 x_di 9 x_di 5 x_di 1 x_fc i p_in t p_rd y# p_rs t# p_a8 e l_d6 l_d5 l_d2 l_d0 gnd l_a1 5 vcc l_a9 vdd x_d o22 vcc x_d o9 gnd x_d o0 x_di 26 vcc x_di 13 vdd x_di 0 vcc p_g nt1 gnd p_ad s# p_a1 0 p_cl k p_a7 f l_d11 l_d1 0 l_d8 l_d3 t_m ode # p_r wc# p_a9 p_a4 p_a3 p_a2 g l_d1 5 l_d1 4 l_d1 3 l_d7 vcc vcc p_a6 p_d3 1 p_d3 0 p_d2 9 h l_d2 0 l_d1 8 l_d1 6 l_d1 2 l_d9 p_a5 p_a1 p_d2 8 p_d2 6 p_d2 4 j l_d2 4 l_d2 3 l_d2 1 l_d1 7 vdd vdd p_d2 7 p_d2 3 p_d2 1 p_d2 0 k l_d2 9 l_d2 7 l_d2 6 l_d2 2 l_d1 9 p_d2 5 p_d2 2 p_d1 9 p_d1 8 p_d1 6 l l_we o# l_d3 1 l_d3 0 l_d2 8 vcc gnd gnd gnd gnd gnd gnd vcc p_d1 7 p_d1 4 p_d1 3 p_d1 2 m l_bw 0# l_oe 0# l_w e1# l_oe 1# l_d2 5 gnd gnd gnd gnd gnd gnd p_d1 5 p_d1 0 p_d1 1 p_d9 p_d8 n l_bw 3# l_ad s# l_b w2# l_b w1# s_cl k gnd gnd gnd gnd gnd gnd vdd p_d7 p_d6 p_d4 p_d5 p l_bw 5 l_b w4 l_b w7 l_b w6 vdd gnd gnd gnd gnd gnd gnd p_d0 t_d0 p_d1 p_d3 p_d2 r l_d3 3 l_d3 4 l_d3 6 l_d3 5 l_d3 2 gnd gnd gnd gnd gnd gnd t_d1 0 t_d4 t_d3 t_d2 t_d1 t l_d3 7 l_d3 8 l_d3 9 l_d4 1 vcc gnd gnd gnd gnd gnd gnd vcc t_d9 t_d7 t_d6 t_d5 u l_d4 0 l_d4 2 l_d4 3 l_d4 6 l_d4 7 t_d2 0 t_d1 5 t_d1 2 t_d1 1 t_d8 v l_d4 4 l_d4 5 l_d4 8 l_d5 1 vdd vdd t_d1 9 t_d1 6 t_d1 4 t_d1 3 w l_d4 9 l_d5 0 l_d5 2 l_d5 6 l_d5 7 pm_ do[1] t_d2 5 t_d2 1 t_d1 8 t_d1 7 y l_d5 3 l_d5 4 l_d5 5 l_d6 1 vcc vcc pm_ den o t_d2 4 t_d2 3 t_d2 2 aa l_d5 8 l_d5 9 l_d6 0 m_cl ki m0_t xd0 nc le_# syn ci pm_ di[1] pm_ di[0] pm_ deni ab l_d6 2 l_d6 3 m0_t xen m0_c rs_d v gnd m2_l nk vcc m3_ crs _dv vdd m5_l nk vcc m6_t xd1 m8_t xd0 gnd m9_t xd1 vcc m10_ rxd1 vdd m11_ txd0 vcc nc gnd m_m dc le_# clk o le_s ync o pm_ do[0] ac m0_l nk m0_t xd1 m0_r xd1 m1_t xen m2_t xd1 m2_ rxd 1 m3_t xd1 m4_l nk m4_ rxd 1 m5_t xd0 m6_t xen m7_l nk m7_c rs_d v m8_r xd1 m9_t xen m10_ txen m10_ rxd0 m11_ rxd1 nc nc nc nc nc m_m dio le_d i le_d o ad nc m0_r xd0 m1_t xd1 m2_t xen m2_c rs_d v m3_t xd0 m4_t xen m4_ crs _dv m5_t xd1 m5_ rxd 0 m6_c rs_d v m7_t xen m7_r xd1 m8_c rs_d v m9_t xd0 m9_r xd0 m10_ txd0 m11- txen m11_ rxd0 nc nc nc nc nc nc nc ae nc m1_l nk m1_r xd0 m2_t xd0 m3_l nk m3_ rxd 1 m4_t xd1 m4_ rxd 0 m5_ crs _dv m6_l nk m6_r xd1 m7_t xd1 m8_l nk m8_t xen m9_l nk m9_r xd1 m10_ txd1 m11_ lnk m11_ crs_ dv nc nc nc nc nc nc nc af m1_t xd0 m1_c rs_ dv m1_r xd1 m2_r xd0 m3_t xen m3_ rxd 0 m4_t xd0 m5_t xen m5_ rxd 1 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m8_t xd1 m8_r xd0 m9_c rs_ dv m10_ lnk m10_ crs_ dv m11_ txd1 nc nc nc nc nc nc nc 1 234567891011121314151617181920212223242526
mds212 data sheet 12 zarlink semiconductor inc. 1.1 ball-signal assignments signal name ball no. nc d4 reserved c3 agnd a1 reserved b1 avdd c1 t_mode# f5 reserved c2 l_clk d3 l_d0 e4 l_d1 d2 l_d2 e3 l_d3 f4 l_d4 d1 l_d5 e2 l_d6 e1 l_d7 g4 l_d8 f3 l_d9 h5 l_d10 f2 l_d11 f1 l_d12 h4 l_d13 g3 l_d14 g2 l_d15 g1 l_d16 h3 l_d17 j4 l_d18 h2 l_d19 k5 l_d20 h1 l_d21 j3 l_d22 k4 l_d23 j2 l_d24 j1 l_d25 m5 l_d26 k3 l_d27 k2 l_d28 l4 l_d29 k1 l_d30 l3 l_d31 l2 l_d32 r5 l_d33 r1 l_d34 r2 l_d35 r4 l_d36 r3 l_d37 t1 l_d38 t2 l_d39 t3 l_d40 u1 l_d41 t4 l_d42 u2 l_d43 u3 l_d44 v1 l_d45 v2 l_d46 u4 l_d47 u5 l_d48 v3 l_d49 w1 l_d50 w2 l_d51 v4 l_d52 w3 l_d53 y1 l_d54 y2 l_d55 y3 l_d56 w4 l_d57 w5 signal name ball no. l_d58 aa1 l_d59 aa2 l_d60 aa3 l_d61 y4 l_d62 ab1 l_d63 ab2 m0_lnk ac1 m_clki aa4 m0_txen ab3 m0_txd1 ac2 m3_txd1 ac7 m3_txd0 ad6 m3_crs_dv ab8 m3_rxd1 ae6 m3_rxd0 af6 m4_lnk ac8 m4_txen ad7 m4_txd1 ae7 m4_txd0 af7 m4_crs_dv ad8 m4_rxd1 ac9 m4_rxd0 ae8 m5_lnk ab10 m5_txen af8 m5_txd1 ad9 m5_txd0 ac10 m5_crs_dv ae9 m5_rxd1 af9 m5_rxd0 ad10 m6_lnk ae10 m6_txen ac11 m6_txd1 ab12 m6_txd0 af10 m6_crs_dv ad11 signal name ball no.
mds212 data sheet 13 zarlink semiconductor inc. m6_rxd1 ae11 m6_rxd0 af11 m7_lnk ac12 m7_txen ad12 m7_txd1 ae12 m7_txd0 af12 m7_crs_dv ac13 m7_rxd1 ad13 m7_rxd0 af13 m8_lnk ae13 m11_txd1 af19 m11_txd0 ab19 m11_crs_dv ae19 m11_rxd1 ac18 m11_rxd0 ad19 nc af20 nc ae20 nc ad20 nc ac19 nc af21 nc ae21 nc ad21 nc ac20 nc af22 nc ae22 nc af23 nc ac21 nc ad22 nc ae23 nc ab21 nc ac22 nc ad23 nc ae24 nc af24 signal name ball no. nc af25 nc ae25 nc aa22 nc ac23 nc ad24 nc af26 nc ae26 nc ad26 nc ad25 m_mdio ac24 l_we0# l1 l_oe0# m2 l_we1# m3 l_oe1# m4 l_bw0# m1 l_bw1# n4 s_clk n5 l_bw2# n3 l_bw3# n1 l_ads# n2 l_bw4# p2 l_bw5# p1 l_bw6# p4 l_bw7# p3 t_d15 u23 t_d14 v25 t_d13 v26 t_d12 u24 t_d11 u25 t_d10 r22 t_d9 t23 t_d8 u26 t_d7 t24 t_d6 t25 signal name ball no. t_d5 t26 t_d4/bs_rdyop r23 t_d3/bs_psd r24 t_d2/bs_swm r25 t_d1/bs_rw r26 t_d0/bs_bmod p23 p_d0 p22 p_d1 p24 p_d2 p26 p_d3 p25 p_d4 n25 p_d5 n26 p_d6 n24 p_d7 n23 p_d8 m26 p_d9 m25 p_d10 m23 p_d11 m24 p_d12 l26 p_d13 l25 p_d14 l24 p_d15 m22 p_d16 k26 p_d17 l23 p_d18 k25 p_d19 k24 p_d20 j26 p_d21 j25 p_d22 k23 p_d23 j24 p_d24 h26 p_d25 k22 p_d26 h25 p_d27 j23 signal name ball no.
mds212 data sheet 14 zarlink semiconductor inc. p_d28 h24 p_d29 g26 p_d30 g25 p_d31 g24 p_a1 h23 p_a2 f26 p_a3 f25 p_a4 f24 p_a5 h22 p_a6 g23 p_a7 e26 p_clk e25 p_a8 d26 p_a9 f23 m0_txd0 aa5 m0_crs_dv ab4 m0_rxd1 ac3 m0_rxd0 ad2 nc ad1 nc ae1 m1_lnk ae2 m1_txen ac4 m1_txd1 ad3 m1_txd0 af1 m1_crs_dv af2 m1_rxd1 af3 m1_rxd0 ae3 m2_lnk ab6 m2_txen ad4 m2_txd1 ac5 m2_txd0 ae4 m2_crs_dv ad5 m2_rxd1 ac6 m2_rxd0 af4 signal name ball no. m3_lnk ae5 m3_txen af5 p_a10 e24 p_rst# d25 p_rwc# f22 p_ads# e23 p_rdy# d24 p_brdy# c25 p_blast# c26 nc b26 nc b25 p_int d23 p_reqc c24 p_gntc a26 p_req1 a25 p_gnt1 e21 p_csi# a24 reserved b24 reserved c23 x_fci d22 x_dclki b23 x_dni c22 x_di0 e19 x_di1 d21 x_di2 a23 x_di3 b22 x_di4 a22 x_di5 d20 x_di6 c21 x_di7 b21 x_di8 a21 x_di9 d19 x_di10 c20 x_di11 b20 signal name ball no. x_di12 a20 x_di13 e17 x_di14 c19 x_di15 d18 x_di16 b19 x_di17 a19 x_di18 c18 x_di19 d17 x_di20 b18 x_di21 a18 x_di22 c17 x_di23 b17 x_di24 d16 x_di25 a17 x_di26 e15 x_di27 c16 x_di28 b16 x_di29 a16 x_di30 d15 x_di31 c15 x_fco b15 x_dclko a15 x_deno d14 x_do0 e14 x_do1 c14 x_do2 a14 m8_txen ae14 m8_txd1 af14 m8_txd0 ab13 m8_crs_dv ad14 m8_rxd1 ac14 m8_rxd0 af15 m9_lnk ae15 m9_txen ac15 signal name ball no.
mds212 data sheet 15 zarlink semiconductor inc. m9_txd1 ab15 m9_txd0 ad15 m9_crs_dv af16 m9_rxd1 ae16 m9_rxd0 ad16 m10_lnk af17 m10_txen ac16 m10_txd1 ae17 m10_txd0 ad17 m10_crs_dv af18 m10_rxd1 ab17 m10_rxd0 ac17 m11_lnk ae18 m11_txen ad18 x_do3 b14 x_do4 b13 x_do5 a13 x_do6 c13 x_do7 d13 x_do8 a12 x_do9 e12 x_do10 b12 x_do11 d12 x_do12 c12 x_do13 a11 x_do14 b11 x_do15 c11 x_do16 a10 x_do17 d11 x_do18 b10 x_do19 c10 x_do20 a9 x_do21 b9 x_do22 e10 signal name ball no. x_do23 d10 x_do24 c9 x_do25 a8 x_do26 b8 x_do27 d9 x_do28 c8 x_do29 a7 x_do30 b7 x_do31 c7 l_a3 d8 l_a4 a6 l_a5 b6 l_a6 c6 l_a7 d7 l_a8 a5 l_a9 e8 l_a10 b5 l_a11 a4 l_a12 d6 l_a13 c5 l_a14 b4 l_a15 e6 l_a16 d5 l_a17 c4 l_a18 b3 l_a19 a3 l_a20 a2 reserved b2 vcc e7 vcc e11 vcc e16 vcc e20 vcc g5 vcc g22 signal name ball no. vcc l5 vcc l22 vcc t5 vcc t22 m_mdc ab23 le_di ac25 le_clko ab24 le_synci aa23 le_do ac26 le_synco ab25 t_d31/pm_d0[1] w22 t_d30/pm_d0[0] ab26 t_d29/pm_deno y23 t_d28/pm_d1[1] aa24 t_d27/pm_d1[0] aa25 t_d26/pm_deni aa26 t_d25 w23 t_d24 y24 t_d23 y25 t_d22 y26 t_d21 w24 t_d20 u22 t_d19 v23 t_d18 w25 t_d17 w26 t_d16 v24 vcc y5 vcc y22 vcc ab7 vcc ab11 vcc ab16 vcc ab20 vdd e9 vdd e18 signal name ball no.
mds212 data sheet 16 zarlink semiconductor inc. vdd j5 vdd j22 vdd n22 vdd p5 vdd v5 vdd v22 vdd ab9 vdd ab18 gnd e5 gnd e13 gnd e22 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 signal name ball no. gnd p16 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd ab5 gnd ab14 gnd ab22 signal name ball no.
mds212 data sheet 17 zarlink semiconductor inc. 2.0 ball-signal descriptions the type of all pins is cmos. all input pins are 5 volt tolerance. all output pins are 3.3 cmos drive. cpu bus interface ball no(s) symbol i/o description g24, g25, g26, h24, j23, h25, k22, h26. j24, k23, j25, j26, k24, k25, l23, k26, m22, l24, l25, l26, m24, m23, m25, m26, n23, n24, n26, n25, p25, p26, p24, p22 p_d[31:0] i/o-ts, u processor da ta bus- data bit [31:0] e24, f23, d26, e26, g23, h22, f24, f25, f26, h23 p_a[10:1] input /output ?u process address bus-address bit [10:1] d25 p_rst# input-st process bus ? master reset f22 p_rwc# input/output- ts, u process bus ? read/write control programmable polarity e23 p_ads# input /output- ts, u process address strobe d24 p_rdy# output-od - ts, u process bus ? data ready c25 p_brdy# input- ts, u process bus ? burst ready c26 p_blast# input- ts, u process bus ? burst last d23 p_int output process bus ? interrupt request programmable polarity e25 p_clk input process bus ? bus clock a24 p_csi# input- u chip select c24 p_reqc input bus request from cpu - only using in debug mode when system is unmanaged. a26 p_gntc output bus grant to cpu - only using in debug mode when system in unmanaged. a25 p_req1 input/output bus request from secondary mds212 to primary mds212. only us ing in debug mode when system in unmanaged.
mds212 data sheet 18 zarlink semiconductor inc. note: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver u = internal weak pull-up ts = tri-state st = schmitt trigger e21 p_gnt1 input/output bus grant to secondary mds212 from primary mds212. only us ing in debug mode when system is unmanaged. frame buffer interface ball no(s) symbol i/o description ab2, ab1, y4, aa3, aa2, aa1, w5, w4, y3, y2, y1, w3, v4, w2, w1, v3, u5, u4, v2, v1, u3, u2, t4, u1, t3, t2, t1, r4, r3, r2, r1, r5, l2, l3, k1, l4, k2, k3, m5, j1, j2, k4, j3, h1, k5, h2, j4, h3, g1, g2, g3, h4, f1, f2, h5, f3, g4, e1, e2, d1, f4, e3, d2, e4. l_d[63:0] i/o-ts, u frame buffer ? data bit [63:0] a2, a3, b3, c4, d5, e6, b4, c5, d6, a4, b5, e8, a5, d7, c6, b6, a6, d8. l_a[20:3] output frame buffer ? address bit [20:3] d3 l_clk output frame buffer clock n2 l_ads# output frame buffer address status control p3, p4, p1, p2, n1, n3, n4, m1 l_bw[7:0]# output frame buffer individual byte write enable [7:0] m3, l1 l_we[1:0]# output frame buffer write chip select [1:0] m4, m2 l_oe[1:0]# outp ut frame buffer read chip select [1:0] ball no(s) rmii ethern et access ports [11:0] ab23 m_mdc output mii management data clock ? (common for all rmii ports[11:0]) ac24 m_mdio io-ts mii management data i/o ? (common for all rmii ports{11:0]) cpu bus interface (continued) ball no(s) symbol i/o description
mds212 data sheet 19 zarlink semiconductor inc. aa4 m_clki input reference input clock ac18, ab17, ae16, ac14, ad13, ae11, af9, ac9, ae6, ac6, af3, ac3. m[11:0]_rxd [1] input- u ports [11:0] ? receive data bit [1] ad19, ac17, ad16, af15, af13, af11, ad10, ae8, af6, af4, ae3, ad2. m[11:0]_rxd [0] input- u ports [11:0] ? receive data bit [0] ae19, af18, af16, ad14, ac13, ad11, ae9, ad8, ab8, ad5, af2, ab4. m[11:0]_crs _dv input- u ports [11:0] ? carrier sense and receive data valid ad18, ac16, ac15, ae14, ad12, ac11, af8, ad7, af5, ad4, ac4, ab3. m[11:0]_txe n output ports [11:0] ? transmit enable af19, ae17, ab15, af14, ae12, ab12, ad9, ae7, ac7, ac5, ad3, ac2. m[11:0]_txd[ 1] output ports [11:0] ? transmit data bit [1] ab19, ad17, ad15, ab13, af12, af10, ac10, af7, ad6, ae4, af1, aa5. m[11:0]_txd[ 0] output ports [11:0] ? transmit data bit [0] ae18, af17, ae15, ae13, ac12, ae10, ab10, ac8, ae5, ab6, ae2, ac1. m[11:0]_lnk input- st, u ports [11:0] -- link status xpipe interface i/o function b23 x_dclki input xpipeflow data clock input c22 x_deni input xpipeflow data enable input d22 x_fci input xpipeflow flow control input c15, d15, a16, b16, c16, e15, a17, d16, b17, c17, a18, b18, d17, c18, a19, b19, d18, c19, e17, a20, b20, c20, d19, a21, b21, c21, d20, a22, b22, a23, d21, e19. x_di[31:0] input xpipeflow data input bits [31:0] a15 x_dclko output xpipeflow data clock output b15 x_fco output xpipeflo w flow control output d14 x_deno output xpipeflow data enable output frame buffer interface (continued) ball no(s) symbol i/o description
mds212 data sheet 20 zarlink semiconductor inc. c7, b7, a7, c8, d9, b8, a8, c9, d10, e10, b9, a9, c10, b10, d11, a10, c11, b11, a11, c12, d12, b12,e12, a12, d13, c13, a13, b13, b14, a14, c14, e14. x_do[31:0] output xpipeflow data output bit [31:0] port mirroring aa26 pm_deni input- ts, u port mirroring data enable input aa25, aa24 pm_di [1:0] input- ts, u por t mirroring input data bit [1:0] y23 pm_deno output port mirro ring data enable output ab26, w22 pm_do[1:0] output port mi rroring output data bit [1:0] test facility (sharing pins with other functions and for testing purpose only) f15 t_mode# io-ts, u test pin ? set mode upon reset, and provides test status output. w22, ab26, y23, aa24, aa25, aa26, w23, y24, y25, y26, w24, u22, v23, w25, w26, v24, u23, v25, v26, u24, u25, r22, t23, u26, t24, t25, t26, r23, r24, r25, r26, p23 t_d[31:0] output test output led interface ac25 le_di input, u led serial data input stream aa23 le_synci# input, u led in put data stream envelop ab24 le_clko output le d serial interface output clock ac26 le_do output led serial data output stream ab25 le_synco# output led outp ut data stream envelop system clock, power, and ground pins n5 s_clk input system clock at 100 mhz e9, e18, j5, j22, n22, p5, v5, v22, ab9, ab18 vdd power +2.5 volt dc supply e7, e11, e16, e20, g22, l22, t22, y22, ab20, ab16, ab11, ab7, y5, t5, l5, g5 vcc power +3.3 volt dc supply frame buffer interface (continued) ball no(s) symbol i/o description
mds212 data sheet 21 zarlink semiconductor inc. note: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver u = internal weak pull-up ts = tri-state st = schmitt trigger e5, e13, e22, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, ab5, ab14, ab22 vss power ground ground c1, c1 avdd[1:0] analog power used for the pll a1, a1 avss[1:0] analog ground used for the pll bootstrap pins p23 bs_bmod input cpu bus mode must be set to 0 r26 bs_rw input cpu read/write control polarity selection default=1 0=r/w#; 1=w/r# r25 bs_swm input switch mode: default=1 0=managed mode 1= unmanaged r24 bs_psd input primary device enable pin default=1 0=secondary 1=primary r23 bs_rdyop input option of merge the p_rdy# and p_brdy# as one pin default=1 0=merged pin 1=separated pins frame buffer interface (continued) ball no(s) symbol i/o description
mds212 data sheet 22 zarlink semiconductor inc. 3.0 the media access control (mac) the mds212 mac contains twelve fast ethernet macs, defined by the ieee standa rd 802.3 csma/cd. each fast ethernet mac is connected to a physical layer (phy) via the reduced media independent interface (rmii). the mac sublayer consists of a transmit and receive section and is responsible for data encapsulation/ decapsulation. data encapsulation/decapsulation involv es framing (frame alignment and frame synchronization), handling source and destination addresses, and detecting physical medium transmission errors. the mac also manages half-duplex collisions, including collision avoidance and contention resolution (collision handling). the mds212 includes an opti onal mac control sublayer (?mac control ?) used for ieee flow control functions. during frame transmission, the mac transmit section encapsulates the data by prepending a preamble and a start of frame delimiter (sfd), inserts a destination and source address, and appends the frame check sequence (fcs) for error detection. in vlan aware switches, the ma c inserts, replaces, or remo ves vlan tags from these frame formats based on instructions from the search engine. when necessary, the mac regenerates the frame check sequence and performs ?padding? for frames of less than 64 bytes in size. during frame reception, the mac receive section verifies that the crc is valid, de-ser ializes the data, and buffers the frame into the receive fifo. the mac then signals the frame engine, using receive direct memory access (rxdma), that data is available in the fifo and is ready for storage. 3.1 mac configuration mac operations are configured through the global device configuration register ( dcr2) and/or the mac control and configuration registers (ecr0, ecr1), defined in the register definition section of the mds212 data sheet. the default settings for autonegotiation, flow contro l, frame length, and duplex mode may be changed and configured by the user on a per-port basis, either in hardware or software. 3.2 the inter-frame gap the inter-frame gap (ifg), de fined as 96 bit times, is the interval between successive ethernet frames for the mac. depending on traffic conditions, the measurement reference for the ifg changes. if a frame is successfully transmitted without a collision, the ifg measurement starts from the deassertion of the transmit enable (txen) signal. however, if a frame suffers a collision, the if g measurement starts from the deassertion of the carrier sense (crs) signal. 3.3 ethernet frame limits a legal ethernet frame size, defined by the i eee specification, must be between 64 and 1518 by tes, referring to the packet length on the wire. for transmitting or forwardi ng frames whose data lengths do not meet the minimum requirements, the mac appends extra bytes (padding) from the pad field. frames, longer than the maximum length may either be forwarded or discarded, depending on the register configuration. although the mac may be configured to forward oversized frames in the device configuration register (dcr2), the frame buffers? maximum size of 1536 bytes cannot be exc eeded. for vlan aware systems, the ma ximum frame size is increased from 1518 bytes to 1522 bytes to acco mmodate the 4-byte vlan tag. 3.4 collission handling and avoidance if multiple stations on the same network attempt to tr ansmit at the same time, interference can occur causing a collision. the mac monitors the carrier sense (crs) signal to determine if the medium is available before attempting to transmit data . if the transmission medium is busy, the mac defers (delays) its own transmissions to decrease the load on the network. th is is called collision avoidance. if a collision occurs, the mac ceases data transmission after the first 64 bytes of data and sends the jam sequence to notify all connected nodes of a collision. this jam se quence will persist for 32 bit times. the jam sequence is a 32 bit predetermined pattern used to notify others of a coll ision on the network. if a collision occurs during preamble generation, or withi n the first 64 bytes, the transmitter waits until the preamble is comple ted and then ?backs off?
mds212 data sheet 23 zarlink semiconductor inc. (that is, stops transmitting) for a spec ific period (defined by the ieee 802.3 binary expo nential backoff algorithm) before sending the jam sequence and rescheduling transmission. a frame with a size of no less than 96 bits (64 bits of preamble and 32 bits of jam pattern), is sent to guarante e that the duration of the co llision is long enough to be detected by the transmitting ports involved. 3.5 auto-negotiation the default value of the mds212 mac enables auto-negotia tion. the default value is overwritten if the phy lacks the ability to support auto-negotiation, which is ascertaine d through its respective management interface, rmii. the auto-negotiation process detects the different modes of op eration (i.e. speed selection, duplex mode) supported by the system at the other end of the link segment. upon power on/res et, the phy generates a special sequence of fast link pulses (flps) to begin auto-negotiation. the mds 212 mac, supporting auto-negotiation, reads the results of the operation from the mac configuration registers. 3.6 vlan support virtual local area networks (vlans) assemble a gro up of independent ports (and/or mac addresses) to communicate as if they were on the same physical lan segment, without being restricted by the physically connected hardware. the ports are logically grouped together by vlan identifiers (vlan ids). the mds212 implements a mac address-based classification that associates each vlan id with its mac address in the switch database memory (sdm) for purposes of aging out, or replacing, old vlans. the mds212 mac recognizes vlan-tagged frame formats. during transmission the mac inserts (or extracts) the 4-byte vlan tag and regenerates the frame check sequen ce for the transmitted frame. vlan support requires an increase in the maximum legal frame size, which is set in the device configuration register (dcr2), from 1518 to 1522 bytes. during transmission, if the mac is required to remove the vlan tag from a 64-67 byte rx frame, the mac will append extra bytes (pad) to form a 64 byte frame. 3.7 mac control frames mac control frames, as defi ned by the ieee, are used for specific control functi ons within the mac control sublayer ?mac control.? similar to data frames, cont rol frames are also encapsulated by the csma/cd mac, meaning that they are prepended by a preamble and start of frame delim iter and appended by a frame check sequence. these frames may be distinguished from other ma c frames by their length/type field identifier (88.08h). the control functions are distinguished by an opcode contained in the first two bytes of the frame. upon receipt, mac control parses the incoming frame and determines, by looking at the opcode and the mac address, whether it is destined for the mac (a data frame) or for a specific function within mac control. af ter performing the specified functions, the mds212 discards all mac control frames it receives, regardless of the port configuration. these control frames are not forwarded to any other port and are not used to learn source addresses. 3.8 flow control flow control reduces the risk of data loss during long bursts of activity, by saturating the buffer memory with backlogged frames. the mds212 supports two types of fl ow control: collision-based for half-duplex mode and ieee 802.3x flow control for full duplex mode. in bo th cases, the mds212 recognizes congestion by constantly monitoring available frame buffer memory. when the amount of free buffer space has been depleted, the mds212 initiates the flow control mechanism appropriate to the current mode of operation. setting the flow control (fc_enable) bit in the mac port configuration register (e rc1) turns this operation on, thereby initiating pause frames or applying back pressure flow control when necessary.
mds212 data sheet 24 zarlink semiconductor inc. 3.9 collision-based flow control collision-based flow control, also referred to as backpre ssure flow control, inhibits frame reception for ports operating in half-duplex mode by ?jamming? the link. when the free buffer space drops below a user-defined buffer memory threshold, the mds212 sends a jam sequence to al l non transmitting ports, after approximately eight bytes of payload data has been received, to generate a collision. the jam sequence is a predefined serial data stream sent to all ports to indicate that there has been a collision on the network. these ports will delay (defer) the transmission of data onto the network until the sequence has been completed. 3.9.1 ieee 802.3x flow control ieee 802.3x flow contro l reduces network congestion on ports that are operating in full duplex mode using mac control pause frames and is managed by the flow co ntrol management registers. the full-duplex pause operation instructs the mac to enable the reception of frames with a destination address equal to a globally assigned 48-bit reserved multicast address of 01-80- c2-00-00-01. these pause frames are subsets of mac control frames with an opcode field of 0x0001 and are used by the mac control to request that the recipient stops transmitting non-control frames for a specific period. the pause timer is loaded from the pause frame and is started upon the reception of a pause frame. it will request a length of time for which it wishes to inhibit data frame transmission. in general, the ieee stand ard allows pause frames longer than 64 bytes to be discarded or inte rpreted as valid. the mds212 recognizes all mac control frames (pause frames) between 64 and 1518 bytes long. any pause frames presented to the mac outside of these parameters are discarded. 4.0 frame engine description the frame engine is the heart of the mds212. it coordina tes all data movements, ensuring fair allocation of the memory bandwidth and the xpipe bandwidth. when frame data is received from a mac port, it is te mporarily stored in the mac rxfifo until the frame engine moves it to the chip?s external memory one granule (128-b yte-or-less fragment of frame data) at a time. the frame engine then issues the search engine a switching reques t that includes the source mac address, the destination mac address, and the vlan tag. after the search engine has resolved the address, it transfers the information back to the frame engine via a switching response that in cludes the destination port and frame type (e.g., unicast or multicast). when the destination port is idle, the frame data is fetche d from the memory and is written to the destination port?s mac txfifo. however, when the destination port is busy transmitting another frame, the frame engine writes a transmission job that includes a frame handle for future id entification. these transmissi on jobs are stored in the destination port?s transmission scheduling queues (txq). th ere are four txqs per port, one for each priority class. when the destination port is ready, the frame engine sele cts the head-of-line job from a txq. the frame, specified by the job, will be fetched from the memo ry and will be written to the mac txfifo. for unicast frames, if the destination de vice is local (i.e., the destination por t is located in the same device), the frame engine writes a job into the destination port?s transmission scheduling queue (txq). the transmit dma (txdma) moves the frame data to the ma c txfifo once the frame?s transmissi on job is selected for transmission. if the destination device is remote (i .e., the destination port is located on a nother device, and can only be reached through the xpipe), all signalling between the two devices are sent as xpipe messages. the frame engine sends a scheduling request message via the xpipe to the destination port. this message asks the remote frame engine to write a job into the destination port?s txq. when that job is selected, the remote frame engine sends a data request message via the xpipe to the local frame engine. reception of a data request message triggers the forwarding engine module to forward the frame data to the destination port, one granule at a time through the xpipe until the end of file (eof) safely a rrives at the remote port?s mac txfifo.
mds212 data sheet 25 zarlink semiconductor inc. for multicast frames, the process is slightly different. the frame engine uses the vlan index, which is part of the search result, to identify the destination ports. for local destination ports, the frame engine writes a job to each port?s txq. when a transmission job is selected, the txdma moves data from the memory to the mac txfifo. multicast frame data is sent multiple times, until all local destination ports? requests are satisfied. for a vlan that includes remote destination ports, the multicast frame data is forwarded once through the xpipe and then stored in the remote device?s memory. the remote frame engine processes this multicast frame as if it came from a local port. a frame is stored in a frame data buffer (fdb) until it is transmitted. fdbs are external, located in a mds212?s frame buffer memory. to keep track of per-frame cont rol information, the frame engine maintains one frame control buffer (fcb) per frame. fcbs are internal. since the frame engine does not access the external memory for frame control info rmation, this conserves memory ban dwidth for better performance. as a frame lives through its lifecycle, its status is updated in the fcb. the fcb also contains vital frame information, such as destination port and length. there is a one-to-one correspondence between the fcb and the fdb: fcb#274 contains information about the frame stor ed in fdb#274. an fcb/fdb pair is called a ?frame buffer,? or simply a ?buffer.? the number 274 is called the handle or the buffer handle. the frame engine takes care of the distribution and the releasing of buffers. it also keeps bu ffer counters to ensure no port or single type of traffic occupies too many buffers. the receiving dma (rxdma) moves frame data from the ma c rxfifo to the fdb. before the rxdma writes frame data into the fdb, it must obtain a free buffer handle from the buffer manager. a free buffer handle points to an empty or released frame buffer, ensuring that no stor ed frame data will get overwritten. after the eof has been safely stored in the fdb, it writes the frame information to the fcb and issues a switching request to the search engine. if the frame is found to be bad (e.g., bad crc), the buffer handle will be released and nothing will be written to the search engine or the fcb. this returns the bu ffer back to circulation and the frame is discarded. the rxdma can fail to obtain a free buffer handle for two reasons. all buffers are currently occupied, or the received frame is a multicast frame and the multicast bu ffer quota is exhausted. in either case, the rxdma will discard the frame, without getting a handle. if set, the re gister bit dcr2[26], ipmc, enables ip multicast privileges. if enabled, the rxdma discards regular multicast frames if the multicast forwarding fifo?s occupancy exceeds the programmable threshold (see register mbcr[21:20], mcth ). an ip multicast frame is discarded only when the multicast frame?s forwarding fifo is full. 4.1 transmission scheduling there are four transmit scheduling queues (txq) per port, on e for each priority. when a port is ready to transmit, when the previous frame finished transmitting, the port control module notifies the frame engine. the frame engine selects one txq out of the four priority queues, depending on the frame?s arrival time and weighted round robin state (refer to the qos chapter for more detail). it reads an entry from the se lected transmission scheduling queue, and if the source port of the selected frame is lo cal, a transmission request is issued to the local txdma module. if, on the other hand, the source port is remo te, the data request message is forwarded across the xpipe and subsequently arrives at the forwarding engine. the four transmit scheduling queues per output port a llows the frame engine to perform weighted round robin (wrr) to provide quality of service (qos). the search engine classifies the frames into four internal priorities, q0, q1, q2, and q3, in decreasing priority. the 802.1p priority bits are mapped to the internal priorities by a programmable mapping, accessibl e via register avtc. the user can prog ram the queue weights via register axsc, and thereby control the relative rates of the four internal-priority tagged frames. the maximum txq lengths are programmable from 128 entries to 1024 entries per queue. 48 txqs are located in the external memory. the maximum queue lengths and th e base memory addresses are accessible by the register group {cpuircmd, cpuirdat, cpuirrdy}, under type qcnt.
mds212 data sheet 26 zarlink semiconductor inc. 4.2 buffer management the buffer manager is responsible for the free handle allocation, buffer usage monitoring, buffer release, and fcb access control. free handles point to buffers that are not occupied by a frame. these free buffers can be allocated to a new frame received by the rxdma or the mrp. when the frame engine is done processing a frame, its handle is released to the free handle pool. the free handle pool must be initialized via the regi ster group cpuircmd, cpuirdat, cpuirrdy, type bmct, before device operation. the buffer manager control table (bmct) is the pool of free handles. at reset, the bmct is empty. prior to device operation, free handles must be written to the bmct. the user must write the integers {0,1,2,3, ? k-1} to the bmct one-at-a-time, where k is the maximum number of buffers. the value of k depends on the external memory size and partition, and it can be 128, 256, 512, or 1024. if all buffers are used, no more frames can enter the devi ce. the frame engine keeps buffer counters that limit the number of buffers occupied by frames destined for each output port. if a buffer counter exceeds a programmable threshold, its associated output port is ?blacklisted.? enteri ng frames destined to this output port are discarded, until the counter goes below the threshold. this threshold is programmed via registers bct and bchl. these counters prevent complete depletion of buffers due to an overlo aded port, thus allow frames destined for non-congested ports to enter the system. this effect ively avoids head -of-line blocking. the frame engine also keeps a buffer counter for multicast traffic types. the buffers occupied by incoming multicast frames are li mited. this prevents multicast frames from blocking unicast ones from entering the system. the threshold for multicast traffic types is programmed via register mbcr. 5.0 frame buffer memory 5.1 frame buffer memory configuration the mds212 system utilizes external sram for its frame buffer memory configuration, where the size of memory supported is ? mb, 1mb and 2mb configurations. the fo llowing table shows four memo ry configuration examples for the mds212 system: sram type one bank two bank address size address size 64kx32 l_a[18:3] ?mb l_a[19:3] 1m 128kx32 l_a[19:3] 1mb l_a[20:3] 2m table 1 - type and size of memory chips
mds212 data sheet 27 zarlink semiconductor inc. the following figure shows the connections between the fr ame buffer memory and the mds212 for one-bank and two-bank memory configurations: figure 3 - frame buffer memory configuration 5.2 frame buffer memory usage the mds212 supports two switching modes: manage d and unmanaged. the following tables describe frame buffer memory usage for managed and unmanaged modes of operation, respectively: note: fe = frame engine, se = search engine table 2 - frame buffer memory usage for managed mode description unit size unit count total size reference by frame data buffer (fdb) 1.5 kbytes 256 to 1 k 384 k bytes to 1.5 m bytes fe 1 transmission queue 4 bytes x 128 k to 4 bytes x 1 k 48 (4 level priority) 24 kbytes to 192 kbytes (at 4 level priority) fe 1 cpu/hisc mailing list 32 bytes to 64 bytes (programmable) 128 to 1 k 4 k bytes to 32 kbytes (at 32 bytes each) cpu, hisc & se 1 vlan table 8 bytes x 4 k 1 32 kbytes hisc & se 1 vlan mac table 8 bytes to 32 bytes x 2 k 1 16 kbytes to 64 kbytes hisc & se 1 sram 64kx32 sram 64kx32 sram 64kx32 sram 64kx32 sram 64kx32 sram 128kx32 sram 128kx32 sram 128kx32 mds212 mds212 two bank 1m 64kx32 one bank 0.5m 64kx32 l_d[31:0] l_a[18:3] l_a[18:3] l_d[63:32] one bank 1m 128kx32 two bank 2m 128kx32 l_a[19:3] l_a[19:3] l_d[31:0] l_d[63:32] l_a[19:3] l_a[19:3] ce ce l_a[19:3] l_a[20] mds212 mds212 l_d[63:32] l_d[63:32] l_d[31:0] l_d[31:0] l_a[18:3] ce l_a[19] l_d[63:32] l_d[63:32] l_a[18:3] l_a[18:3] l_d[31:0] l_d[31:0] ce sram 128kx32 sram 128kx32 sram 64kx32 sram 64kx32
mds212 data sheet 28 zarlink semiconductor inc. note: fe = frame engine, se = search engine in unmanaged mode, the system does not support vlan features. thus, vlan related tables are not required. table 3 - frame buffer memory usage for unmanaged mode 5.2.1 memory allocation of a managed system in a managed system, the frame buffer memory is partit ioned into five segments: frame data buffers (fdbs), transmission queues, mai ling lists, vlan, and mct vlan association tables. 5.2.1.1 frame data buffers the frame data buffers (fdbs) accommoda te the incoming data frames and part ition them into da ta blocks, where each block occupies 1.5 k by tes. the number of data blocks in a fdb is configured by sett ing the valu e in the register fcbsl[9:0]. since mds212 supports up to 2 m by tes memory, the maximum numbe r of data blocks is 1 k. note: the fdb must start at location 0. description unit size unit count total size reference by frame data buffer (fdb) 1.5 kbytes 256 to 1 k 384 k bytes to 1.5 m bytes fe transmission queue 4 bytes x 128 k to 4 bytes x 1 k 48 (4 level priority) 12 (1 level priority) 24 kbytes to 192 kbytes (at 4 level priority) fe hisc mailing list 32 bytes to 64bytes (programmable) 128 to 1k 4 k bytes to 32 kbytes (at 32 bytes each) hisc & se
mds212 data sheet 29 zarlink semiconductor inc. figure 4 - memory map of managed system 5.2.1.2 transmission queues the transmission queues controls the scheduling of the tran smission ports, where each of these ports can support up to 4 priorities. there are up to 48 individual transmission queues, which represents 4 priorities for each of the 12 ports of the mds212. the number of priorities is programmable. thus, the mds212 may be configured for 12, 24, 36, or 48 transmission queues and may support 1, 2, 3, or 4 priority levels, respectively. the size per transmission queue is 128, 256, 512, or 1024 entr ies and may be setup during the initialization phase. the search engine maintains the contents of each queue , where each queue consists of transmission priorities. each double word (4-bytes) entry contains a fdb handle, which points to the corresponding frame in the buffer. 5.2.1.3 mailing list the mailing list provides a communication channel between the hisc and cpu in managed mode. the size of a mail entry varies, ranging from 32 to 64 bytes, which is determined by the initialization setup. when the cpu or the hisc writes mail, the cpu/hisc can obtain a free mail by the register afml that contains the addresses of free mail. conversely, when the cpu or hisc reads its mail , the cpu/hisc accesses the mail by the register ambx that contains the address of a cpu/hisc mail. all of the mail registers are maintained by the hardware. 5.2.1.4 vlan table the vlan table associates the ports to their respective vlans, using the vlan id. the table contains 4 k vlan entries, where each entry contains 8 bytes of information . the size of the vlan table is 32 kb (4kx8b). the base address of the vlan table is specified by the vidb in the vtbp bit [5:0]. note: the vlan table must be located at the 32 k boundary. fdb frame data buffers (1.5kb x # of frame buffers) transmission queues (4x12=48 queues) (each entry = 1dw) (# entry of queue = 128 to 1k) cpu/hisc mailing list (# entry = 128 to 1k) (each mail entry = 32 bytes to 64 bytes) vlan table (4k entry, 8b/entry) vlan mac table (2k entry) (each entry = 256, 128 or 64 bit) byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 byte 7 63 0 0 fdb block must start from 0 programmable size 32kb 16, 32 or 64kb max 1/2mb, 1mb or 2mb programmable size
mds212 data sheet 30 zarlink semiconductor inc. 5.2.1.5 vlan mac association table the vlan mac table (vlan mct) associates each por t?s mac address with its re spective vlan. the table comprises of 2048 entries, one entry per mac address. each vlan mac entry is mapped to each bit associated with a vlan specified by the vlan index. the size of the table is defi ned by two bits in the vtbp register and de pends on the system co nfiguration (e.g. the number of vlans supported in the syste m). each entry may consist of 256, 12 8 or 64 bits (one bit per vlan). the total size of the vlan mac table may be 16, 32, or 64 kb. the vmacb field in the register vtbp specifies the base address. note: the vlan mac table must be located at the 16 k boundary. 5.2.2 unmanaged system memory allocation since an unmanaged system does not support vlan op eration, the vlan and vlan mac tables are not required. only the frame data buffers, transm ission queues, and hisc mailing li sts are allocated in system memory. figure 5 - memory map of an unmanaged system 5.3 the frame memory interface 5.3.1 local memory interface each frame within the mds212 is allocated its own buffer memory. the primary function of the frame buffer memory is to provide a temporary buffering space for bo th received and transmitt ed frames, as well as frames waiting in the transmission queue. the actual usage depend s on the frame type to be tr ansmitted, either unicast or multicast and the relationship between the source and destination ports. the buffer memory also, contains other control structures including stacks, queues, other control tables. the buff er memory may be configured for 128 k, 256 k, 512 k, 1024 k bytes dep ending on the a pplication of the system design er. the mds212 local memory interface supports up to 2 m bytes of sbram. the switch manager cpu initializes the local buffer memory during the switch initialization phase/process. fdb frame data buffers (1.5kb x # of frame buffers) transmission queues (4x12=48 queues) (each entry = 1dw) (# entry of queue = 128 to 1k) hisc mailing list (# entry = 128 to 1k) (each mail entry = 32 bytes to 64 bytes) byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 byte 7 63 0 0 fdb block must start from 0 programmable size max 1/2mb, 1mb or 2mb programmable size
mds212 data sheet 31 zarlink semiconductor inc. 6.0 search engine the search engine is responsible for determining the destination information for all packet traffic that enters the mds212. the results from all address or vlan searches are passed to the frame engine to be forwarded, or on to the hisc block for further processing. either way, the result messages provide all the needed information to allow the destination block to process the packet. the search engine has been optimized for high throughput searching, utilizing the integrated switch database memory (sdm). the internal sdm cont ains up to 2 k mac control table (mct) entries. these mct entries are searched utilizing one of four hashing algorithms that ca n be selected. this provides the capability of changing the search hashing to optimize the hash tables based on the tr affic patterns in a given network. for example, if a company gets all their network interf ace cards (nic) from one vendor, then the source and destination mac addresses will have common fields. this can lead to inefficient search hashing. with 4 different hash selections that utilize different parts of the address fields, and can be 8, 9, or 10 bits in length, the hashing algorithm that works best for a user?s network can be selected (by testing each hash algorithm). figure 6 - typical packet header information layer 1 preamble sfd data efd packet destination mac address destination mac address source mac address source mac address vlan tag 0x800 ver ihl typ of serv total length identifier flg fragment offset time to live protocol header checksum ip source address ip destination address options + padding source port # destination port # sequence number acknowledgement number checksum urgent pointer options + padding data offset reserved uaprsf window layer 2 layer 3 layer 4 enet 2 header ip 64 bytes tcp/ip header header
mds212 data sheet 32 zarlink semiconductor inc. the search process begins when the frame engine transfer s the first 64 bytes of a packet header to the search engine. these bytes are parsed to extract the information needed to perform the search for the mct entries that match the source and destination mac address, genera te the search hash keys, and lookup vlan membership and other packet status information. 6.1 layer 2 search process when the mds212 is in either a ?forwarding? state (able to forward packets) or a ?learning? state (able to learn new addresses), the search engine is capable of performing address searches. the search process begins when packet header information is transferred to the search engine from the frame engine. the search engine first checks to determine if the mds212 is configured to support virtual local area networks (vlan). if vlans are enabled, the search engine will search for both the destination mac address, to get destination resolution information, and the source mac address, to get the port?s vlan membership and verify the validity of the port?s vlan membership. if vlans are disa bled, the search engine will search for the destination and source mac addresses but will not do a vlan table check. 6.1.1 vlan unaware when vlans are not enabled or configured, the search engine will search the internal switch database memory for an mct that matches the destination mac address. when a match is found, the search engine will check to ensure that the destination address is not to be filtered before sending a search result message back to the frame engine to start the packet forwarding process. at the same time, a search for the mct that matches the source mac address is also performed. if no match is found for the source address, then the source mac address needs to be learned. 6.1.2 vlan aware when vlans are enabled and configured, the search engine will begin searching for the destination mct and the source mct. if a matching mct is found for the source address, then no learning is required, and the search engine will check the vlan membership of the source port. if the source port is a member of the vlan, and the destination port is also a member of the vlan, then a normal response message will be passed to the frame engine. if the source port is not a va lid member of the vlan, or the destination port is not a member of the vlan, then the search engine will decide to forward the packet or drop the packet depending upon a user defined configuration. then it will send a message to the hisc to allow the hisc to resolve the issue. 6.2 address and vlan learning address learning can be performed by either the hisc or the search engine and can be enabled or disabled. the global learning control is set in the device configuratio n register (dcr2). the global learning disable (gln) bit controls whether learning is active or disabled, and can be set during initial power up configuration, or by an external cpu before it begins modifying the sdm. it is necessary for an external cpu to disable learning before updating or modifying mct entries. this prevents the intern al learning process from modifying mct entries without the cpu?s knowledge. when learning is globally enabled, by the search engine not finding a match to a source address search, it can create a new mct with the necessary information, and then notify the hisc that a new address has been learned. if the search engine request queue becomes 3/4th full, the search engine will ignore address learning until the request queue is less full. in that case, packets are fo rwarded as usual, and a message is sent to the hisc requesting that the hisc learn the new address. if th e search engine request queue is too full, and the hisc request queue is full, then no learning will take place. when two mds212 chips are connected, and configured to operate with synchroni zed mct entries, the hisc processor has the ability to send a request to the search engine, instructing it to learn a new address received from
mds212 data sheet 33 zarlink semiconductor inc. the other mds212. the hisc processor can also use this method to make simple edits to the mct entries for port changes (i.e., source mac address is now connected to a different port on the mds212). 6.3 flooding and packet control packets, for which there are no matching destination mct en tries, are by default floo ded to all output ports. this can result in broadcast storms and cause the number of flooded packets to increase rapidly. the mds212 provides the user a means for setting a level of flooding, by provid ing a flooding control register (fcr). the fcr allows the user to define a time base (100 us to 12.8 ms) during which packet flooding at each output port will be counted. three separate flood control fields allow the user to specify flooding limits for: ? unicast to multicast (flooded) packets per source port ? unicast to cpu packets per chip ? multicast to cpu packets per chip during the time base period, three separate counters at each port count the number of packets meeting the flood control types. once a counter exceeds the allowed quantity, the search engine will then discard the packet and any other packets of that type that enter the port during th e remainder of the time base period. when the time base period is completed, the three flood counters at each port are reset, and the counting process starts over. the flooding control register is global for setting the limits on all register ports, but the individual ports have separate counters to keep track of the number of flooded. 6.4 packet filtering packet filtering occurs during the address search phase. for static source or destination mac address filtering, there is a corresponding bit in the mct entry that tells the search engine that the source or destination packet is to be filtered. when a match is found to a destination mac address sear ch, the ?destination filter? (d) field in the mct is checked to determine if the destination address is to be filt ered. if ?d? is asserted, the search engine discards the packet by sending a message to the frame engine telling it to release the frame control buffer (fcb) where the packet has been stored in the frame buffer memory. the packet thereby deleted from memory. when a match is found to a source mac address search, the ?source filter? (f) field in the mct is checked to determine if the source address is to be filtered. if ?s? is asserted, then the search engine discards the packet by sending a message to the frame engine telling it to release the fcb for the packet. 6.5 address aging entries in the mct database are removed if they have not been used within a user selectable timeframe. this aging process is handled by inspecting a single mct entry duri ng each clock period. if the entry is valid and subject to aging, an aging flag in the mct entry is cleared. if the aging flag is already set to zero during the inspection, an aging message is sent to the hisc processor to delete and free up the aged mct entry. each time an mct entry is matched by way of a search engine, source search process, the aging flag is asserted to restart the aging process for that entry. some entries may be static and not subject to aging. these mct entries have a status field that identifies them as being static, and will therefore always have their aging flag asserted. the network manager, using zarlink software, establishes static entries during a switch config uration session.
mds212 data sheet 34 zarlink semiconductor inc. 6.6 ip multicast the search engine supports the ability of the mds212 to provide ip multicast by identifying internet group multicast protocol (igmp) packets when parsing the packet header information provided by the frame engine. igmp packets are identified when the source mac address is 01-00-5e-xx-xx-xx and the protocol field has the value of 2, or when the sour ce ip address is 224.0.0.x. when an igmp packet is identified, the search engine searches for the source address mct entry, and then passes a message to the hisc to allow it to setup or tear down the ip mult icast session. ip mu lticast sessions are treated as vlans and use one of the 256 regular vlan entries. 7.0 the high density in struction set computer (hisc) 7.1 description the high density instruction set cpu (hisc) is specific ally designed to implement highly efficient management functions for the mds212 sw itching hardware, minimizing the management activity intervention during frame processing. the hisc services management requests ba sed on an event- driven approach. management requests can be generated from either the management cpu or t he switching hardware. the hisc is also designed with a powerful instruction set and dedicated hardware interfac es for packet processing and transmission to provide high performance packet transfers between the cpu interface and the switching hardware. 7.2 hisc architecture the hisc is designed with an advanced pipeline architec ture that combines the advantages of both risc and vliw architectures. the hisc core co mbines a rich instruction set with 88 general-purpose registers and support for multiple-way jump. the 88 registers are divided into three parts, eight common general-purpose registers and two banks of 40 registers for two different task contexts. a ll registers are directly connec ted to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction execution. each hisc instruction may ha ve up to three sub- instruct ions, which can be executed in one clock cycle. the resulting architecture is more code efficient, while achieving through puts up to ten times faster than a cisc processor or up to three times faster than a risc processor. for a mds212 running at 100 mhz, the hisc can produce up to 300 mips processing power. 7.3 hisc operations with an event-driven operation model, upon the request from either the search engine or external management cpu, the hisc dynamically manages and maintains the switch database including mac address entries, vlan, and mac-vlan association tables. the hisc also prov ides an external management cpu a high-speed data communication interface, so management packets can be transmitted to or received from the network. in general, the service request is received from one of four different sources: ? messages from the management cpu ? requests from the switching hardware (search engine) ? real time clock ? interrupts to the management cpu the hisc performs the following major operations: ? resource initialization ? resource management ? switching database management ? send and receive frames for management cpu
mds212 data sheet 35 zarlink semiconductor inc. 7.3.1 resource initialization the hisc initializes all internal data structures including th e mail box and switching database data structures, which are used by the management cpu, hisc, and switching hardware. 7.3.2 resource management the hisc can enforce a replacement policy when the number of free data structures for new mac address entries is lower than the predefined threshold. 7.3.3 switching database management one of the major manage ment tasks required of the hisc is to crea te, delete, and modify mac address entries upon requests from the search engine or management cpu. generally, the search engine performs the learning of new mac addresses id entified in the packet st reams. for a single mds212 system , the hisc simp ly informs the management cpu regarding the newly learned mac addresses. the hisc may also create, delete, or modify the mac address entries based on the requests from the management cpu. for a multi-ds system, the hisc is response fo r synchronizing the s witching databases. in addition to the mac address entries, the hisc also maintains the following database information required for switching: ? create, delete and modify vlan table in the switching database. ? create, delete and modify mac vlan table in the switching database. ? create, delete and modify ip multicast entries in the switching database. 7.3.4 send and receive frames for management cpu the hisc delivers bdpu, snmp, and other frames to an d from the management cpu. in unmanaged mode, the hisc also responds to interrupts destined to the management cpu. 7.4 communication between hisc and switching hardware high-speed communication channels are required to pr ovide fast message deliveries between the hisc and switching hardware. two high-performance fifos prov ide the required communication channels. they are between the hisc and the frame engine, and between the hisc and search engine. 7.4.1 communication between search engine and hisc the first high-speed fifo is used by the search engi ne to send messages, management requests or received packets, to the hisc. whenever a message is sent to th e fifo, the hisc is notified of the new event. each message may contain up to two command codes, processed by the hisc sequentially. the hisc can also request for the search engine to do operations such as search or learn via a hisc i/o interface. after processing the requests, the search engine sends the re sponse back to the hisc via the fifo. 7.4.2 communication between hisc and frame engine the second high-speed fifo is used by the hisc for sending data transfer requests to the frame engine. whenever a packet-forwarding request is received from the management cpu, the hisc forwards the request to the frame engine via the fifo. to alleviate the worklo ad of the management cpu, certain management packets can be processed by the hisc, and then forwarded to the frame engine for transmission via the fifo.
mds212 data sheet 36 zarlink semiconductor inc. 7.5 communication between management cpu and hisc the hisc serves as an intermediary communication channel between the switching hardware and the external management cpu. there are two communication mechanis ms provided for messages exchanged between the management cpu and hisc. 7.5.1 cpu-hisc communication using queues the first communication mechanism is a pair of input and output queues between the hisc and management cpu. the management cpu input/output queue is a very efficient mechanism for a single 32-bit data exchange between the hisc and management cpu. in general, a manageme nt frame, i.e., bridged data protocol units (bdpu), is forwarded directly from the hisc to the management cpu via the cpu output queue. small management requests, less than 24 bits, are de livered to the hisc via the cpu input queue. 7.5.2 mailbox the second communication mechanism is a hardware mailbox that can support variable size messages, exchanged between the management cpu and the hisc. a major use of the mailbox is to exchange information required for updating the switching database. 7.5.2.1 cpu-hisc mail when the management cpu sends a mail message to the hi sc, the cpu acquires an address of a free mail from the free mail list (via register afml), it writes the mail c ontent to the given memory addr ess. afterward, it sends the mail to the hisc via the mailbox access (ambx) regist er. whenever a management mail message is received, an event is generated to inform the hi sc to process the mail message. 7.5.2.2 hisc-cpu mail when a mail message arrives from the hisc, the mailbox hardware sends an interrupt, namely ?mail arrive? (mail_arr), to the cpu. the cpu can then access the mail via the mailbox access register (ambx). at this point, the cpu reads the mail handle and retrieves th e contents of the mail from the ambx register.
mds212 data sheet 37 zarlink semiconductor inc. 8.0 the xpipe the xpipe provides a high-speed link between systems util izing two mds212 devices. the xpipe incorporates a 32-bit-wide data pipe, with a high-speed point-to-point connection, and a fu ll-duplex interface betweendevices. while operating at a 100 mhz, this interface can provide 3.2 g bits per second (gbps) of bandwidth per pipe in both directions. 8.1 xpipe connection figure 7 - xpipe system block diagram for the mds212 the xpipe interface employs 32 data signals and three control signals for each direction. the pin connections between two mds212 devices are depicted in figure 7. these 32 data signals form a 32- bit-wide transmission data pipe that carries xpressflow messages to and from the devices. the direction of all signals are from the source to the target device, except for the flow control signal, which sends messages in the opposite direction; from the target to the source. the three control signals consist of a transmit clock signal, a transmit data enable signal, and a flow control signal. the transmit clock signal (x_dclko), provides a synchr onous clock to sample the data signals at the target device. the source device provides the transmit data enable signal (x_deno) that envelops an entire xpipe message (including the header and the payload) and is used to identify the message boundary from the received data stream. the timing relationship between the data, clock, and data enable signals are described in the xpipe timing (section section 8.2 ?xpipe timing? ?). transmit fifo x_do[31:0] x_dclko x_deno x_fci x_di[31:0] x_dclki x_deni x_fco receive fifo xmit ctrl recd ctrl source target receive fifo x_di[31:0] x_dclki x_deni x_fco x_do[31:0] x_dclko x_deno x_fci transmit fifo recd ctrl xmit ctrl target source mds212 mds212
mds212 data sheet 38 zarlink semiconductor inc. table 4 - summary description of th e source and target end signals the flow control signal (x_fc) monitors the state of the receiving queue at the target end to prevent xpipe message loss. when the target end does not have enough space to accommodate an entire xpipe message, the target device sends a xoff signal by driving the x_fco signal to low. the source device will stop further transmission until the x_fci signal asserts the xon st ate, which is an active high (see table 4). the xpipe message header provides the payload size, type of message, routing information, and control information for the xpipe incoming message. the routing information includes the device id and port id. the header size is dependent upon the message types and may be 2 to 4 words in length. figure 8 - xpipe message header 8.2 xpipe timing the source device generates the x_clko signal to provide a synchronous transmit data clock. the receiver will then sample the data on the falling (negative) edge of the clock, as shown in figure 9. to identify the boundary between the xpipe messages and the data stream, the source device uses the x_den signal to envelop the entire xpipe message. that is, a rising (positive) edge at the beginning of the first double word (4 bytes) and a falling (negative) edge at the beginning of the last double word of an xpipe message as shown in figure 9. note: the negative edge does not occur at the end of the last double word, but instead, at the beginning of the last double word. this allows xpipe messages to be sent consecutively (back-to-back). signal name description source end target end x_do[31:0] x_di[31:0] 32-bit-wide transmit data bus - includes an xpipe message header and followed by the data payload. x_dclko x_dclki transmit clock - synchronous data clock provided by the source end. x_deno x_deni transmit data enable - provided by the source end to envelop the entire xpipe message. x_fci x_fco flow control signal - a flow control pin from the target end to signal the source end to active xon/xoff. 2-4 words header 0-64 words payload xpipeflow message header data payload
mds212 data sheet 39 zarlink semiconductor inc. figure 9 - basic timing diagram of xpipe 9.0 physical layer (phy) interface the physical layer interface is designed to interface zarlin k semiconductor chipsets to a variety of physical layer devices. reduced media independent interface (rmii) is used for 10/100 interfaces. the chip ball names for the mac use m as the first letter of the name, followed by th eir pin number, and then their function. m1_rxd0 refers to mac port 1, receive data 0, of the receive data pair. 9.1 reduced mii (rmii) the mds212 implements the reduced media independent interface (rmii) signals, ref_clk, crs_dv, rxd [1:0], tx_en, and txd [1:0], defined in section 5 of the rmii consortium specification. the purpose of this interface is to provide a low cost alternative to th e ieee 802.3u [2] mii interface. under ieee 802.3u [2], an mii comprised of 16 pins for data and control is defined. in devices incorporating many macs or phy interfaces such as switches, the number of pi ns can add significant cost as the port counts increase. the mds212 offer 12 or 24 ports, in one or two devices respectively. at 6 pins per port and 1 pin per switch asic, the rmii specification saves 119 pins plus the extra power and ground pins to su pport those additional pins for a 12 port switch asic. architecturally, the rmii specification provides for an additional reconciliation layer on either side of the mii but can be implemented in the absence of an mii. the manageme nt interface (mdio/mdc) is assumed to be identical to that defined in ieee 802.3u [2]. the rmii supports both 10 and 100 mbps data rates across a two bit transmit data (txd) path and a two bit receive data (rxd) path. the rmii uses a single synchronous clock reference sourced from the media access controller (mac), or an external clock source, to the physica l layer (phy). doubling the clock frequency to 50 mhz allows a reduction of required data and control signals, thereby providing a low cost alternative to the ieee std 802.3u media independent interface (mii). the rmii functions to ma ke the differences between copper and optical phys transparent to the mac sublayer. x_clki/o x_deni/o x_di/o[31:0] cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 ......... last cycle idle d word 0 d word 1 d word 2 d word 3 ................ d word n ................ ................ *1 note 1: positive edge at the beginning of the first double word. negative edge at the beginning of the last double word.
mds212 data sheet 40 zarlink semiconductor inc. the rmii specification has the following characteristics: ? it is capable of supporting 10 mbps and 100 mbps data rates. ? a single clock reference is sourced from the mac to phy (or from an external source). ? it provides independent 2 bit wide (di-bit) transmit and receive data paths. ? it uses ttl signal levels, compatible with common digital cmos asic processes. table 5 - rmii specification signals 10.0 the control bus the cpu interface, or control bus, provides the communication path between the system cpu and all other key components within the switch (i.e. the hisc). it operates in two modes: managed mode, where it utilizes an external cpu, and unmanaged mode, where an external cpu does not exist. in managed mode, the cpu interface provides the communication path between the systems? external cpu and the hisc, frame buffer memory (sram) or another mds212. see figure 10. figure 10 - cpu interface conf iguration in managed mode in unmanaged mode, the cpu interface provides the communication path between the switch devices and flash memory, and between any two mds212 switches. see figure 11. signal name direction (with respect to the phy) direction (with respect to the mac) ref_clk input or output synchronous clock reference for receive, transmit and control interface m[0:11]_crs_dv input carrier sense/receive data valid m[0:11]_rxd[1:0] input receive data m[0:11]_tx_en output transmit enable m[0:11]_txd[1:0] output transmit data m[0:11]_rx_er input (not required) receive error control bus mds212 mds212 cpu flash memory
mds212 data sheet 41 zarlink semiconductor inc. figure 11 - control bus conf iguration in unmanaged mode 10.1 external cpu support the control bus comprises of a 32-bit wide cpu bus and supports big and little endian cpu byte ordering. the standard microprocessors supported include: ? intel 486 cpus ? motorola mpc860 and 801 cpus. ? intel i960jx cpu ? mips processor with minimum conversion. 10.1.1 power on/reset configuration on power-up, the five bootstrap bits, on table 6, are used. 10.1.2 cpu bus clock interface the cpu interface allows the cpu bus clock to operate at clock rates diff erent from the system clock rate. the cpu bus clock rate is al ways less than or equal to the system clock rate. table 6 - bootstrapping options name default functional description bs_bmod 1 bus mode must be 0 bs_rw 1 selects r/w control polarity 0=r/w# 1=w/r# bs_swm 1 switch mode (onl y in managed mode) 0=managed mode 1=unmanaged mode bs_psd 1 primary device enable (only in unmanaged mode) 0=secondary mode 1=primary mode (the arbiter is activated in the chip with primary device.) bs_rdyop 1 option of merger the p_rdy# and p_brdy# 1=seperated p_rdy# and p_brdy# pins 0=merged p_rdy# and p_brdy# pin control bus mds212 mds212 flash memory primary dev arbitrator secondary dev
mds212 data sheet 42 zarlink semiconductor inc. 10.1.3 address and data buses the cpu interface provides separate, non-multiplexed address and data buses. the data bus is a synchronous, 32-bit bus that can receive 16 or 32-b it wide data. the flash memory uses a 16-bit data bus. the data bus supports 32 bit wide data for managed and unmanaged modes. the address bus supports 10 [10:1] address bits for managed and unmanaged modes. each device occupies 2048 bytes of input/output space. 10.1.4 bus master the nomenclatures ?master? and ?slave? refer to the device that possesses the cpu interface, or control bus, while the designations of ?primary? and ?secondary? refer to the device that possesses the bus arbiter. the primary or secondary device is determined during power on/reset, bootstrap options, while the master or slave device changes dynamically, and will be determined by the arbiter. in managed mode, th e systems? external cpu is th e permanent master device. all other devices (e.g,. the mds212) are designated as slave devices only. in unmanaged mode, the arbiter (located within the primary device) selects one of the devices as the master. note: in unmanaged mode, the primary device may be the master or the slave. the master device is the bus master (controls the bus), while t he other device is a slave device. 10.1.5 input/output mapped interface the systems? external cpu a ccesses the switch devices? lo cal memory using single-read/ write or burst- read/write i/o cycles. burst i/o operatio ns with auto address incrementing uses a 32 -byte write data buffer and a 32-byte cache read data buffer. 10.1.6 interrupt request the cpu interface accepts an interrupt request (irq) from each device connected to the interface, and supports centralized interrupt arbitration and vector response. the interrupt output is an open-drain option with programmable polarity. 10.2 control bus cycle waveforms figure 12 - control bus i/o and flash bus access operations p_clk p_ads# p_rdy# p_a[10:1] p_brdy# p_blast# one-wait state wait read read read read wait wait read read cycle = 8 clks write cycle burst read cycle sample
mds212 data sheet 43 zarlink semiconductor inc. 10.3 the cpu interface in unmanaged mode in unmanaged mode, the hisc processor of the master device communicates with the slave device as a cpu function. three registers and one flag are used to co mmunicate between the hisc processor and the cpu interface. 10.3.1 arbiter the arbiter of the xpressflow mds212 is an internal logi c device used to determine which device will function as the master device. the connections bet ween the master device, slave device, and the cpu are used for debugging purposes only (see figure 13). during power on/reset, the bootstrap pin, bs_psd, determines which device will be the primary and activates the arbiter of that device. at most, three devices, tw o mds212 devices and one cpu, can operate on the cpu interface at the same time. each device may request access to the cpu interface by sending a request signal to the arbiter. the arbiter, then sends a grant signal acknowledging which device has been chosen. figure 13 - block diagram of the arbiter note: in unmanaged mode, the cpu is used only for debugging purposes and cannot be involved in switching decisions or management activities. an arbitrate scheduler, located within the arbiter, decides which device functions as the master device. if the master is the secondary device, the arbiter will send a grant signal and a chip select (p_cs) signal to the device. if the master is the primary device, the grant signal is sent di rectly to the master state machine (msm) by an internal signal. the scheduler then performs a round robin configur ation and allows each device to be the master device. note: during power on/reset, the arbiter always selects the primary device to be master device. only for debug cpu master the state machine arbiter chip select bus request bus grant mds212 master the state machine primary mds212 secondary p_gntc p_reqc p_req1 p_gnt1
mds212 data sheet 44 zarlink semiconductor inc. 10.4 cpu interface in managed mode the cpu slave state machine (ssm) accepts address stro be (p_ads#), chip select (p_cs#), and bus- data ready (p_rdy#) signal s as ready state signals of a cpu cycle. 10.4.1 cpu access the 32-bit cpu bus interface supports both big and little endian cpus. the difference between big and little endian is the byte swapping when cpu write data to external memory. table 7 below summarizes the byte swapping operation and figure 14 illus trates an example of bytes swapping. table 7 - little and big endian byte swapping operation figure 14 - an example of byte swapping 11.0 the led interface 11.1 led interface the mds212 led interface supports the status per port in a serial stream that may be daisy-chained to connect two mds212 chips. daisy-chaining greatly reduces the pi n count and number of board traces routed from the physical layer to the leds, thus simp lifying system design and reducing overall system cost. for a large port configuration such as the 24 in the mds212, a large number of led signals is needed, which may induce noise and layout issues in the system. the led in formation is transmitted in a frame- structured format wit h a synchronization pulse at the start of each frame. if using little endian bit[1] must be ?0? for register of mwars, mrars, mwarb, mrarb no byte swapping for cpu data write in or read out to/from mwdr, mrdr registers if using big endian bit[1] must be ?1? for register of mwars, mrars, mwarb, mrarb automatic byte swapping for cpu data write in or read out to/from mwdr, mrdr registers byte 0 byte 1 byte 2 byte 3 cpu bus internal data bus 31 24 23 16 15 8 7 0 byte 3 byte 2 byte 1 byte 0 31 24 23 16 15 8 7 0
mds212 data sheet 45 zarlink semiconductor inc. figure 15 - led interface connections to provide the port status information from our mds212 chips via a serial output channel, five additional pins are required. ? le_clko - at 12.5 mhz ? le_synci/o - a sync pulse -- defines the boundary between frames ? le_di/o - acontinuous serial stream of data for all status leds which re peat once every frame time a low cost external device (i.e., a 44-pin fpga-like device ) decodes the led framed data and drives the led array for display. this device may be customiz ed for different system configurations. the port status of the mds212 is transmitted to an exte rnal decoder via a serial output channel. in the mds212, we support cascading of this serial output channel between tw o devices. one mds212 is configured as the master, this initiates the start of led information frames, and seri alizes information bits. the mds212 slave repeats the information sent from the master and appends its own information bits. to cascade these two devices, we will need to extend the number of led pins from 3 to 5. figure 15 shows 2 led interfaces are cascaded and the connections between the mds212s, led decoder and led display. 11.1.1 function description the led interface employs the following signals: table 8 - led signal names and descriptions signal name description master device slave device le_clko led clock-synchronous led clock provided by the slave device to led decoder at the system clo ck divided by 8(~12.5mhz). le_syni le_syno a synchronous pulse--defines the boundary between frames. the length of each led data frame is about 256-bits that shift out by led_clk per bit. le_di le_do a continuous serial stream of data for all status leds which repeat once every frame time. mds212 le_synco le_do master mds212 slave led decoder led display le_clko le_synco le_do le_di le_synci
mds212 data sheet 46 zarlink semiconductor inc. 11.1.2 port status in the mds212, each port consists of 8 different led status, represented by separate bits: 1. flow control 2. transmitting data 3. receiving data 4. action (txd or rxd) 5. link up/down 6. speed 7. full duplex/half duplex 8. collision. in addition to the 12 ports of the mds212, three extra use r-defined status sets may be sent through the led serial channel for debugging or other applications, where each user-defined status set is also represented by 8 bits. 11.1.3 led interface time diagram the master needs to shift out (16)*8 status bits periodic ally((12 port status +4 reserved)*8). thus, slave needs to shift out (16)*8 + (16)*8 status bits, which incl udes the status of the master device and itself. the status of each port will be sampled by the led state machine every 20.5 s, the time period of the frame. that is, each led data frame length equals (256)x 80nsec. each frame is divided into two sub- frames: a master and a slave sub-frame. furthermore, each su b-frame is partitioned into 16 slots (12 mac ports and 4 reserved slots) and each slot will carry 8 status bits. figure 16 shows the signal from the slave chip to led decoder. figure 16 - time diagram of led interface led_clki/o led_syni/o led_di/o cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 *1 master dev sub-frame 16 slots slave dev sub-frame 16 slots one frame 256x80nsec cycle #0 cycle #7 cycle #8 cycle #9 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 po p1 bit 0 bit 1 1* one pulse for every 256 cycles
mds212 data sheet 47 zarlink semiconductor inc. 12.0 data forwarding protocol and data flow 12.1 data forwarding protocol 12.1.1 frame reception for normal frame reception, a 128-byte bl ock of frame data is stored in the rx fifo. this block may be shorter if an end of frame (eof) arrives. at that point, the rxdma will request the use of the internal memory bus. when this memory request is granted, the rxdma will move the blo ck from the rxfifo to the frame data buffer (fdb). the service discipline is round robin for the 100/10 mbps po rts. after the entire frame is moved to the frame data buffer (fdb), a switch request will be sent to the search engine (reference search engine section) 12.1.2 unicast frame forwarding for forwarding of the unicast frame, the search engine fi rst resolves the destination device and the destination port, and sends a switch response back to the frame en gine. the frame engine will obtain the type (unicast or multicast), the destination port, and the destination devi ce from the search response. after processing the search response, the frame engine will notify the destination port that it has a frame to forward to the destination port?s txfifo. for local forwarding (e.g., the destination port is in the local device), the frame engine will send the job to the transmission scheduling queue of the destination port. for remote forwarding (i.e., the destination port is in the remote device), the frame engine will create a data forwarding request command message (data_fwd_req), which is sent via the xpipe to the remote device. the remote frame engine, after receiving this data_fwd _req message, will place a job in the transmission scheduling queue of the destination port.
mds212 data sheet 48 zarlink semiconductor inc. the port will serve the next job from the transmission scheduling queue when the following two conditions are met: ? there is room for a 1.5 kbyte frame (a maximum-sized frame) within the txfifo. ? the end-of-frame (eof) of the current frame has arrived at the txfifo. there are four transmission-scheduling queues for each por t, one for each of the four classes of priority. the port will send the jobs to the transmission scheduling queues according to a first in first out (fifo) order. to start data transmission, the port obtains a job from the transmission scheduling queue and notifies the transmit dma (txdma) to move the data from th e fdb to the mac transmit fifo (txfifo) in 128-byte granules (for local forwarding). otherwise, the device sends a data_req co mmand message via the xpipe to the source device to request remote forwarding. the data forwarding engine module in the frame engine of the source device will then forward the frame in 128-byte granules via the xpipe. 12.1.3 multicast frame forwarding after the reception of the switching response, a job is sent to the transmission scheduling queues of the destination ports for local switching. however, for remote switching, one copy of the frame will be forwarded to the remote device in 128-byte granules via the xpipe. this copy of the frame will be sent to the frame data buffer. the frame engine, after the successful reception of this frame, will put jobs in the transmission scheduling queues of the destination ports of its device. when the txfifo is re ady to receive the frame (same as the conditions stated in unicast frame forwarding section), the txdma will forwar d the frame from the fdb to the destination ports in granule form. the maximum size of a granule is 128 bytes. 12.2 flow for data frame the following subsections describe the flow of informati on during transfers of data frames, both unicast and multicast. 12.2.1 unicast data frame to local device in the simplest case, the data frame is destined for a port on the local device. the frame engine moves the received frame to the local fdb. the search engine forms a switch request with the frame header (includes source mac and destination mac) and passes it to the switch e ngine to resolve the destination. the switch engine then provides a destination port address to the frame engine via a switch response message. the frame engine transmits to put a transmission job in transmission schedulin g. after the port is ready to send the frame, the frame engine starts to move the frame to the txfifo. if the mac address cannot be resolved by the switch engine, the hisc and/or the cpu are queried to resolve the address. for an unknown destination mac, the frame will flood the frame into the source vlan domain. 12.2.2 unicast data frame to remote device in another case, the data frame is destined for a port on a remote device. first, the frame engine moves the received frame to the local fdb. a switch request with a frame header (includes source mac and destination mac) is passed to the switch engine to resolve the destination. the switch engine then provides a destination port address to the frame engine. if the address resolution ca nnot be completed by the switch engine, the hisc and/or the cpu are queried. once the addr ess is resolved, the two frame engines perform the following interactive handshaking procedures via the xpipe: ? source frame engine sends a data forwarding reque st message to destination, where the destination frame engine puts a job in the associated transmission scheduling queue. ? when the destination port is ready to send the frame, the destination frame engine send a data request message to the source frame engine. ? after the source frame engine receives the data reque st message, it starts to move the frame in granule form, which is directly written in the destination txfifo.
mds212 data sheet 49 zarlink semiconductor inc. note that, at the remote device, the frame is written into the transmit fifo of the remo te destination port. to reduce the latency, the frame is not stored in the fdb of the remote device again. 12.2.3 multicast data frame in this scenario, we assume that the multicast frame invo lves both local and remote ports. the received multicast frame is written to the local fdb by the frame engine. af ter resolving the destinations, the switch engine provides local destination port addresses and remote port addre sses to the frame engine. if the address resolution cannot be completed by the switch engine, the hisc and/or the cpu are queried. the frame engine pushes the jobs to the corresponding transmission queues (per job per local port). when a local port is ready for this multicast frame, the frame engine moves the frame to the corresponding txfifo. there is a counter to track of the number of copies to be sent. the number is provided by the search engine and the frame engine keeps track of this counter. when a frame is sent, the counter is decreased by one. the fdb will be released when the counter becomes zero. when the destination ports include remote ports, the frame is transferred over the xpipe to the remote frame engine, which writes a single copy of it into the remote fdb. that is, we use double store-and- forward for remote multicast. after receivin g the whole frame, the remote frame engine ut ilizes the control information in the internal header, which indicates the associated destination ports in the remote device to push the jobs into the corresponding transmission queues. when a port is ready for this multicast frame, the frame engine moves the frame to the corresponding txfifo. similarly, the frame en gine also keeps track of the number of copies of a frame to be sent and releases the frame when the counter is reduced to be zero. 12.3 flow for cpu control frame in a managed system, the cpu may transm it or receive cpu control frames, e. g., protocols, snmp frames to/from a mac port via a cpu unicast frame. on the other hand, the cpu may receive a multicast frame from a mac port. moreover, the cpu can transmit a multicast frame to multip le ports. the following four scenarios illustrate the four possible forwarding flows. 12.3.1 cpu transmitting unicast cpu frame the cpu initiates unicast control messages, by first writ ing the frame into the fdb, and then sending a message to the hisc. the hisc forwards a switch response to the frame engine, which transmits the frame to the destination mac port. after receiving switch response, frame engine performs the same unicast forwarding as for unicast data frame. refer to previous subsection for unicast data frame mechanism. 12.3.2 cpu transmitting multicast cpu frame when the cpu sends a multicast control message to the port s, the cpu first writes the frame to the local fdb. the cpu then sends a message to the hisc, which provides a switch response message to the local frame engine. after receiving the switch response, the frame engine perfo rms the same multicast forwar ding as for the multicast data frame. refer to previous subsecti on for multicast data frame mechanism. 12.3.3 cpu receiving unicast frame the receiving cpu frame is moved to the fdb and the fr ame engine forwards a switch request, including the frame header, to the search engine. after the search e ngine decodes the header and determines to forward it to the hisc to process, hisc informs the cpu via a mail , which indicates the handle of the fdb. the cpu then obtains the frame through the mds212. after reading the frame from the fdb, the cpu will inform the hisc to release the fdb. finally, the hisc passes the release command to the frame engine to release the fdb accommodated cpu frame.
mds212 data sheet 50 zarlink semiconductor inc. 12.3.4 cpu receiving multicast frame the mds212 is capable of receiving a multicast packet for a combination of local or remote ports and the cpu. in this case, the received frame includes multicast destination ports on a remote device, and also the cpu. the search engine moves the multicast frame to the fdb and then forms a switch request including the frame header, which it sends to the search engine. since the frame involves the cpu, the search engine passes the request to the hisc for further processing. the hisc informs the cp u via a mail, which indicates the handle of the fdb. in parallel, the search engine sends back a switch response and asks the frame engine to forward the frame to the destinations ports. the frame engine will perform t he same multicast forwarding as mentioned above. the cpu reads the frame from the fdb via the mds212. th e cpu will then inform the hisc to release the fdb. finally, the hisc passes the release command to the frame engine to release the fdb accommodated cpu frame. note: the search engine will not release the fdb until it receives the release signal from the hisc and the counter is reduced to zero. this occurs when the cpu all of the ports have read the frame. 13.0 port mirroring 13.1 features the received or transmitted data of any 10/100 port in any mds212 chip, connected by port mirror signal pins, pm_do and pm_di, can be chosen to be mirrored to the ?mirror port.? the mirror port can be the first port in a mds212 with rmii or a dedicated mirror port with mii, driven by the pin, pm_do[0:1]. once the first rmii port of a chip is selected to be the mirror port, it cannot be used to serve as a data port. the configuration of port mirroring is shown in the following diagram, based on the current evaluation board design. figure 17 - configuration of mirror port for mds212 mds212 mds212 chip 0 pm_do[1:0] pm_deno pm_di[1:0] pm_deni chip 1 pm_do[1:0] pm_deno 4fe rmii 4fe rmii 4fe rmii 4fe rmii 4fe rmii 4fe rmii mii phy port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 mirror port mirror port mirror port -port 0 can be a rmii mirror port and mirror port 1-11 -port 12 can be a rmii mirror port and mirror port 0-11, 13-23 -dedicated mii mirror port can mirror port 0-23
mds212 data sheet 51 zarlink semiconductor inc. 13.1.1 physical pins there are 6 related pins to port mirroring functions: ? pm_di [1:0] port mirror ing input data bit [1:0] receive the mirrored data sign al from the remote mds212. ? pm_deni port mirroring data enable signal for pm_di input provide data enable signal for pm_di signals pm_deni port mirroring data enable signal for pm_di input provide data enable signal for pm_di signals pm_do[1:0] port mirroring output data bit [1:0] tr ansmit the mirrored data signal to remote mds212. pm_deno port mirroring data enable output. provide data enable signal for pm_do signals refer to figure 17 for connecting above pins. 13.1.2 setting register for port mirroring apmr register controls the mirrored port and the designated mirroring port. the definition of the register is shown in section 13.1.2.1 ?apmr- po rt mirroring register? . 13.1.2.1 apmr- port mirroring register the following examples, based on the configuration of figure 17, illustrate how to set the apmr register: example 1: mirroring port 1 to port 0 and mirror transmission direction. for chip 0 set apmr[11:0]=0x002 mirrored port=1 set apmr[12]=0local mirrored port set apmr[13]=0transmission mirroring set apmr[14]=1port 0 is the mirroring port 31 15 14 13 12 11 0 mpo rx/tx l/r mirror port bit [11:0] mirr_port 10/100 port is chosen to be mirrored, (port bit map) bit [12] local/remote indicate the mirrored port fr om local or remote device. 0=local 1=remote note that at most one of bits in bit[11:0] can be set to 1. bit [13] rx/tx whether mirror receiving data or transmitting data 0= transmission mirroring , 1=receiving mirroring bit [14] mp0 mirror to port 0 (default=0) mp0=1 mirror to port 0 mp0=0 mirror not go to por t 0. i.e., to pm_do pins. bit [31:15] reserve
mds212 data sheet 52 zarlink semiconductor inc. for chip 1 don?t care example 2: mirroring port 1 to port 12 and mirror receiving direction. for chip 0 set apmr[11:0]= 0x002mirrored port = 1 set apmr[12]=0 local mirrored port set apmr[13]=1receiving mirroring set apmr[14]=0port 0 is not the mirroring port for chip 1 set apmr[11:0]=0x000 set apmr[12]=1 remote mirrored port set apmr[13]=don?t carebit[13] has meani ng only in the chip of mirrored port set apmr[14]=1port 13 is the mirroring port example 3: mirroring port 1 to mii mirr oring port mirror receiving direction. for chip 0 set apmr[11:0]= 0x002mirrored port = 1 set apmr[12]=0 local mirrored port set apmr[13]=1receiving mirroring set apmr[14]=0port 0 is not the mirroring port for chip 1 set apmr[11:0]= 0x000 set apmr[12]=1 remote mirrored port set apmr[13]= don?t carebit[13] has meaning only in the chip of mirrored port set apmr[14]=0port 13 is not the mirroring port note: the cpu needs to find out the speed of the mirrored port and configures the mirroring port to the same speed. 14.0 virtual local area networks (vlan) 14.1 introduction a virtual lan (vlan) is a logical, independent workgr oup within a network. the members in this workgroup communicate as if they are sharin g the same physical lan segment. vlans are not limited by the hardware constraints that physically connect tr aditional lan segments to a network. as such, vlans can define a network into multiple logical configurations.
mds212 data sheet 53 zarlink semiconductor inc. 14.2 vlan implementation the mds212 based vlan implementation allows up to 256 vl ans in one switch. by using explicit or implicit vlan tagging and the garp/gvrp protocol (defined in i eee 802.1p and 802.1q), vl ans may span across multiple switches. a mac address can belong to multiple vlans, a nd a switch port may be associated with multiple vlans. 14.2.1 static definitions of vlan membership the mds212 defines vlan membership based on ports. port based vlans are organized by physical port numbers. for example, switch ports 1, 2, 4, and 6 can be one vlan, while ports 3, 5, 7, and 8 can be another vlan. broadcasts from servers within each group would only go to the members of its own vlan. this ensures that broadcast storms cann ot cause a network melt-down due to traffic volume. 14.2.2 dynamic learning of vlan membership while port based vlan only defines static binding between a vlan and its port members, the mds212?s forwarding decision needs to be based on the following: ? a destination mac address and its associated port id for a unicast frame, or ? the associated vlan of a source mac address, if the destination mac address is unknown or it is a multicast/broadcast frame. to make valid forwarding and flooding decisions, the mds212 learns the relationship of the mac address to its associated port number and vlan id and builds up the internal switching database at ru n-time for further use. 14.2.3 dynamic learning of remote vlan in addition to adding and deleting vlan member ports through network management tools statically, a mds212 based switch can also support gvrp (garp vlan registra tion protocol). gvrp allows for dynamic registration of vlan port members within a switch and across multiple switches. in addition to supporting the dynamic update of registration entries in a switch, gvrp is also used to communicate vlan registration information to other vlan-aware switches, so that a vlan member can be covered by a wide ra nge of switches in a network. gvrp allows both vlan-aware workstations and switches to issue and revoke vlan memberships. vlan-aware switches register and propagate vlan membership to a ll ports belonging to the active topology of the vlan.
mds212 data sheet 54 zarlink semiconductor inc. 14.2.4 mds212 data structures for vlan implementation figure 18 - data structure diagram 14.2.4.1 vlan id table the vlan id table is used by search engine for unicast frames. the base address of this table is specified by vidb subfield in bit[5:0] of vtbp register. the conten ts of this table are set up by the mds212?s microcode through the command of cpu software at the time of vl an creation and deletion. the vlan id table covers the entire 4 k vlan id space, and is used by the search engine to map the vlan id into an internal vlan index. it also includes port membership and port tagging informati on for each vlan. each vlan id entry is 8 bytes long, and the total size of the vlan id table is 32 kb. the vlan id table must be located at the 32 k boundary. figure 19 - vlan id table fdb frame data buffers transmission queues cpu/hisc mailing list vlan id table (4k entry, 8b/entry) vlan mac table (2k entry, 256/128/64 bit) byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 byte 7 63 0 programmable size 32kb 16, 32 or 64kb max 1/2mv, 1mb, fdb block must start from 0 external ram programmable size (up to the number of supported vlan) or 2mb p11 p23 31 29 28 27 26 25 24 23 22 21 20 30 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 index[3:0] c v index[7:4] t p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 s p13 p12 0 4 byte bit[1:0] p0 vlan status for port 0 bit [0] s this port is a member of this vlan bit [1] t tagout bit[3:2] p1 vlan status for port 1 .... bit [26] v vlan is valid bit [27] c cpu is a member of this vlan bit [31:28] 1st byte: vlan index [3:0], 2nd byte: vlan index [7:4] 0
mds212 data sheet 55 zarlink semiconductor inc. note: p0 to p11 are used to identify the ports on the first chip, while p12 to p23 are used to identify the ports on the second chip. 14.2.4.2 vlan mac table the size of this table is defined by vlms subfield in bi t[8:7] of vtbp register. the base address of this table is specified by vmacb subfield in bit[ 15:9] of vtbp register. the vlan mac table contains all associated vlans for each mac address learned by mds212, and is used by the software to keep tr ack of every mac and its associated vlans. the contents of this table are set up by the search engine at the reception of incoming frames, if the search engine is not fully occupied. when the search engine is too busy handling frame forwarding decisions, microcode in the hisc engine will be assigned the setup new mac to vlan associations. rows in this table can be cleared up by microcode through a cpu software command during vlan deletion or port link down. a row in this table will be cleared and a new bit set up by the mds212?s microcode, when the port change of a mac address is detected. there are a total of 2 k entries in this table, one entry pe r mac. each entry may consist of 256, 128 or 64 bits, one bit per vlan. the total size of the vlan table may be 64, 32, or 16 kb. this table must be located at the boundary of its own table size. figure 20 - vlan mac table 0 1 2 3 . . . . . . . . . . 2k 0 1 2 3 ............................................... 100 256 vlan id mac handle
mds212 data sheet 56 zarlink semiconductor inc. 14.2.4.3 vlan port mapping table (vmap) the vlan port mapping table (vmap) is an internal table within the mds212. it contains 256 entries, one for each vlan, identified by an internal vlan index. this tabl e can be accessed by cpu software through cpuircmd and cpuirdat registers. the contents of this table are set up and maintained by cpu software during vlan creation, deletion and vlan port membership modification. vmap is used by frame engine to forward multicast or destination unknown unicast frames to multiple ports simultaneously. bit [11:0]vlan tag enable [11:0]one bit for each ethernet mac port 0 = disable, 1 = enable bit [12]reserve bit [24:13]vlan port enable [11:0]one bit for each ethernet mac port , identifying the ports associated with each vlan. 0 = disable, 1 = enable bit [25]reserve bit [26]reremote ports enable: indicate some members in the remote device. 0=disable, 1=enable bit [29:31]reserve 14.2.5 port vlan id (pvid) register this register defines the port vlan id (pvid) and priority for each port. pvi d needs to be set up by cpu software, and is used by mds212 to decide the port?s vlan id and priority if the incoming packet is vlan untagged. bit [11:0]:port vlan id (pvid), bit [12]:reserved bit [15:13]:priority bit [31:16]:reserved 15.0 ip multicast 15.1 introduction ip multicast permits an ip host (source) to transmit a single ip packet to multiple ip hosts (receivers). ip multicasting allows a source to send only one copy and the network ensures delivery to each member of the specified multicast group. network bandwidth is allocated more efficiently, as multiple copies of the same frame are not transmitted between common ports. 31 27 26 25 24 13 12 11 0 re vlan port enable [11:0] tag enable [11:0] 31 24 23 16 15 13 12 11 8 7 0 priority port vlan id
mds212 data sheet 57 zarlink semiconductor inc. the packet destined to an ip multicast group address de termines the set of recipien ts. hosts may choose to be members of a number of multicasts, and hence select t he multicast packets they wi sh to receive. they may subscribe or unsubscribe to these multicast groups dyna mically, using the internet group management protocol (igmp) that support automatic multic ast group membership. igmp is configured to create, update, and/or remove dynamic multicast group entries between switches and mu lticast clients and servers. rfc 1112 specifies the protocols and behaviour for ip multicasting. the mds212 supports up to 255 ip multicast groups and treats them as extensions of the vlan operation. no additional hardware is needed, since the igmp operates on the hardware already provided for vlan functionality. igmp packets are identified by the frame engine and are passed to the external cpu for processing, when the destination mac address is 01-00-5e-xx-xx-xx and the protoc ol field value equals 2, or when the destination ip address is 224.0.0.x. the external cpu then instruct s the hisc to setup ip multicast entries for the mac addresses in the switch database memory, the vlan ta ble, and the mct-vlan table. the hisc builds and maintains an mct-vlan and a vlan table for ip multicast groups in the frame buffer memory. when an ip multicast packet is received, it is identified by a specific class of multic ast destination mac addresses, where the high-order bits indicate use of igmp, and the lo w-order bits indicate the sp ecific igmp group identifier. the mds212 searches the mct vlan association table fo r destination mac addresses, using the igmp or the igmp group identifier stored in the mct, to obtain port membership for the ip multicast group. the search engine forwards the packet to each port associated with the ip multicast group. where no address is found, the hisc firmware updates the mct-vlan to include this address. the multicast buffer control register (mbcr) allows the c onfiguration of multicast fram es to be forwarded, the number of buffers reserved for receiving remote multicast frames, the number of multic ast frames allowed, and the multicast forwarding threshold. 15.2 igmp and ip multicast filtering ip multicast filtering optimizes switched network performanc e by limiting multicast packets to only be forwarded to ports containing multicast group membership instead of flooding all ports in a subnet (vlan). the internet group management protocol (igmp) runs be tween hosts and their immediate neighbouring multicast routers. the mechanism of the protocol allows a host to inform its local router that it wishes to receive transmissions addressed to a specific multicast group. routers, also, periodically query the lan to determine if known group members are still active. based on the group membership information, learned from the igmp, a router is able to determine which (if any) multicast traffic needs to be forwarded to each of its ?leaf? subnetwork. multicast routers use this information, in conjunction with a multicast routing protocol, to support ip multicasting across the internet. the mds212 based switch supports ip multicast filtering by passively snooping on the igmp query. the igmp report packets are transferred between ip multicast routers and ip multicast host groups to learn the ip multicast group members within each vlan actively sending out igmp query messages soliciting ip multicast group members. they thus learn the location of multicast ro uters and member hosts in multicast groups within each vlan. since igmp is not concerned with the delivery of ip multicast packets across subnetworks, an external ip multicast router will be needed if the ip multicast packets have to be routed across different ip subnetworks. 15.3 implementation in mds212 the mds212 supports up to 255 ip multicast groups and trea ts them as an extension of the vlan operation. no additional hardware is needed, since ip multicast switch ing/filtering already operates in hardware provided for vlan functionality. igmp packets are identified by the search engine and are passed to the external cpu for processing, when the destination mac address is 01-00-5e-xx-xx-xx and the protoc ol field value equals 2, or when the destination ip address is 224.0.0.x. the external cpu then instructs the hisc to setup an mct entry fo r this ip multicast address
mds212 data sheet 58 zarlink semiconductor inc. in the switch database memory. if this is a new ip multic ast group, it sets up an entry in the vlan port mapping table by itself, whenever an ip multicast data packet (destination mac = 01-00-5e-xx-xx-xx, and destination ip address is within the range of 224.0.1.0 and 239.255.255. 255) is received, the search engine will use the mct table to look up the ip multicast address of the incoming packet. frame engine then will use the result from the search (vlan index) to forward this ip multicast packet to its member ports according to the vlan port mapping table. 15.3.1 mct table the mct table is an internal table within the mds212 chip that has a total of 2k entries. the cpu setups and read the table one entry at a time through microcode in the hisc. there are two types of overlapped mct entries, one used for layer-2 mac address based unicast switching, and the other for ip multicasting. 15.3.1.1 mct structure for unicast frame the mct table is used by the search engine to forward unicast frames. by looking up a destination mac address from this table, the associated port number is found and used for packet forwarding decisions. the content of the table is set up by the search engine at the reception of an incoming frame, if the search engine is not fully occupied. when the search engine is too busy handling fr ame forwarding decisions, microcode in the hisc engine will be assigned to do the learning job by setting up new mac to port associations. an entry in this table can be setup by microcode in hisc through a cpu software command for static layer-2 packet filtering based on either the source or destination address. an entry can be cleared by microcode in the hisc through a cpu software command, during vlan deletion, port link down, or when it is aged out. it will also be cleared and a new one set up when a port change of a mac address is detected. t: time stamp, used for aging. set to 1 afte r mac is found, and cleared to 0 when aged. mac[5:0]: mac address s: source mac address filtering d: destination mac address filtering sp: transmit speed. 0-100 mbps next handle: pointer to the next entry in a hashed link list. byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543 2 1 0 0 mac3 mac2 mac1 mac0 t 4 s p s d port number mac5 mac4 8 next handle 12
mds212 data sheet 59 zarlink semiconductor inc. 15.3.2 mct structure for ip multicast packet an ip multicast entry in the mct table can be setup or torn down by microcode in hisc through a cpu software command for ip multicasting. whenever an ip multicast data packet is received, the search engine will use this table to look up the ip multicast address and vlan id of the incoming packet. if the ip multicast address is found, an internal vlan index from the mct entry will be used by the search engine and frame engine to forward the ip multicast packet to the specific ip multicast group members in a vlan. if not, the packet will be forwarded to the vlan it belongs to. vlan id: the vlan id this ip multicast group is located in. ip[3:0]: ip multicast address vlan index: internal vlan index used to identify this ip multicast group cpu: 1: switch cpu is part of this ip multicast group next handle: pointer to the next entry in a hashed link list. 16.0 quality of service (qos) quality of service (qos) provides the capability to reserv e bandwidth throughout the network. this is particularly useful for sending voice or video over the switched net work. in a switched ethernet environment, this is only possible with resource reservation protocol (rsvp), a layer 3 protocol. in a layer 2 switch, qos, referred as class of service (cos) by the ieee 802 .1q standard, provides th e capability to prioriti ze certain tasks on the network. this is done at the applicatio n level, where applications can set the priority when the frame is created. the mds212 classifying ethernet frames acco rding to their ieee 802.1p /q vlan priorities. there are three bits in the vlan id reserved to designate the priority of a packet. each port stores its transmission jobs into four trans mission scheduling queues, one for each internal priority. before transmitting, a port selects a queue from which a transmission job is read. the transmission job points to a frame stored in memory that is fetche d and transmitted. the four queues, repr esenting four classes of traffic, are selected using a weighted round robin (wrr) strategy. the relative service rates among these queues are programmable such that bandwidth can be allocated accordin g to classes. this ensures that critical applications get a fair share of bandwidth, even when the network is overloaded. the search engine recognizes the ieee 802.1p priority tag and cl assifies each in coming frame into four internal priority classes: p0, p1, p2, and p3, in decreasing priority. sinc e the ieee 802.1p/q allows up to eight priorities, a programmable mapping allows the user to map the 802.1p prio rity to the internal priori ty tag via register avtc. 16.1 weighted round robin transmission strategy frames of four different priorities are transmitted according to a weighed round robin (wrr) strategy. the wrr is a modified form of the fair round-robin strategy, in which the server visits the queues in turn. in a fair round-robin strategy, the server treats all queues equally and visits them with identical frequency. in a wrr, the queues are weighted, i.e., one queue may be visited more frequentl y than another. these weighs are programmable via register axsc, in which the servic e rate ratio betwe en two adjacent classe s of traffic is set. in register axsc, setting qsw0=2, qsw1 =qsw2=1 gives the service ratio 8:2:1: 1, which is a good start for most lan switches. this ratio allocates 67% = 8/12 of bandwidth to p0, 16% = 2/12 of bandwidth to p1, and p2 and p3 each receives 8.3% = 1/12 of bandwidth, assu ming all frames have identical frame length. byte31 30 292827 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10987654323 0 0 ip1 ip0 vlan id 4 c p u vlan index ip3 ip2 8 next handle 12
mds212 data sheet 60 zarlink semiconductor inc. 16.2 buffer management functions the mds212 stores frame data in frame buffers. the numb er of frame buffers in a system is the maximum number of frames a device can store. when all frame buffers ar e used, incoming frames cannot enter the memory and are discarded. without buffer management, a congested port ca uses a backlog of frames that eventually occupy all frame buffers. the mds212 features buffer management functions that prevent a single type of traffic from depleting all frame buffers. the buffer manager limits the number of frames each destina tion port can store, thereby preventing congested ports from occupying all the buffers and blocking incoming frames. the buffer manager examines the destination port of ever y frame stored, and increments a counter associated with this destination port. these buffer counters keep track of the number of buffers occupied by frames destined to each port. if the counter reaches a threshold, incoming frames destined for the associated port will be dropped. this threshold is programmable via register bct and bchl. register bct allows the user to program two thresholds, one high and one low. the user specifies a threshold, high or low, for each port in register bchl. the buffer manager also prevents multicast frames from occupying all frame buffers. a programmable threshold, register mbcr, limits the number of multicast frames stor ed in memory. in another wo rd, buffers are reserved for unicast frames. a multicast forwarding job points to a multicast frame in memory fetched and forwarded by the frame engine across the xpipe to the remote device. the frame engi ne can only forward a handful of multicast frames simultaneously across the xpipe. excess multicast forwarding jobs are stored in an internal fifo, called the mc forwarding fifo. if the mc forwarding fifo is full, incoming multicast frames can no longer be forwarded to the remote device. for these blocked multicast frames, their remote destination ports are discarded. the mds212 has a programmable option to recognize ip mu lticast (ipmc) frames. by default, ipmc frames are treated equally with layer 2 multicast frames. this option gives ipmc privilege, in terms of buffer allocation, over regular layer 2 multicast frames. in a broadcast storm, la yer 2 multicast frames are discarded before ipmc ones. the system has the flexibility to re cognize a programmable ipmc mac ad dress signature, set by registers ipmcas0, ipmcas1, ipmcmsk0, and ipcmmsk1. if a programmable option, dcr2, bit 26, is turned on, the system reserves space in the mc forwar ding fifo for ipmc frames. this ensu res that layer 2 multicast frames do not block ipmc ones 17.0 port trunking port trunking groups a set of 8 mds212 10/100mbps physical ports into one logical link; however, all ports in the trunk group must be within the same access device, and each port can only belong to one trunk group. all ports in the trunk group must belong to the same vlan and share the same mac a ddress. each system can support up to 4 groups. load distribution for unicast and multicast traffic is done based on a hash key, a hash function of the source address and the destination address.
mds212 data sheet 61 zarlink semiconductor inc. 17.1 unicast packet forwarding a trunked port will need to have its ecr1 mac port configuration register set by cpu software to contain its associated trunk group id. later on, when a new source mac address is learned through that port, the trunk group id will be recorded in the mct entry by either the search engine or the microcode in the hisc. the trunk group id will be used for forwarding decision when the destination mct entry of a received packet is found by the search engine, if the status field indicates that the address found is on a trunk group. the trunk group id is used by the search engine, along wi th the ?hash key? (3 bits result of a hash operation between source address and destination mac address), to access a trunk port mapping table entry in the internal ram. each entry in this table contains the device and po rt ids for the physical port us ed to transmit this packet. software needs to set these entries, using tpmxr and tpmt d registers, to distribute the traffic load across the ports in the trunk group. if the source mac address of an incoming packet is on a trunk group (based on the mct information), the receiving port?s tgid will be compared against the trunk group id in the source mct to decide whether the source mac address has moved to another trunk group or not. figure 21 - port mapping table the trunk port mapping table is 32 entries deep (4 groups * 8 hash entries), and each entry is 5 bits wide (1-bit device id, 4-bit port id), as show in figure 21. . . . . . . port id (4bit) 32 entries dev id (1bit) tg provided by search eng tg hash key (2bits) (3bits) hash key=
mds212 data sheet 62 zarlink semiconductor inc. 17.2 multicast packet forwarding for multicast packet forwarding, the destination device mu st determine the proper set of ports to transmit the packet based on the vlan index and hash key, generated by the source search engine. two functions are needed to distribute multicast packets to the appropriate destination ports in a trunk group: 1. selecting a forwarding port per trunk group only one port per trunk group will be used to forward multicast packets. this can be done with a vlan index table and a forwarding port mask table set up by cpu. 2. blocking multicast packet back to the source trunk for multicast forwarding that includes ports in trunk groups in the same device as source port, all ports in the same trunk group at the receiving port must be excluded. othe rwise, this multicast packet will be looped back to the same source trunk group. this is achieved through a tr unk group id register that contains 36 bits (36=12x3). 17.2.1 select one forwarding port per trunk group to forward multicast frames, the frame engine retrieves th e vlan member ports from one of the 256 entries in the vlan port mapping table (vmap) as described in the vlan section. by using the hash key and the forwarding port mask table, the frame engine can obtain the corres ponding fp mask. the final forwarding ports can then be determined by the logical and of the fp mask and the vlan member port bit map. the forwarding port- mask table must be set by the cpu to thkm[0:7] registers befor ehand. the format of this table and the method of setting it up are shown below. figure 22 - forwarding port mask table two restrictions exist in setting up tables: 1. when setting up the vlan port mapping table, all the ports in the trunk group must be set to 1, if the vlan has ports in any trunk group. 2. when setting up the forwarding port mask tabl e, the cpu software picks only one forwarding port per trunk group. 12 bits forwarding port mask registers 3-bit hash key 8 entries in table vlan member port and fp mask forwarding ports cpu sets up this table as follows: 1. set up one entry of the register at a time until table is exhausted. 2. set all bits not in any trunk group to 1. 3. set all bits in the trunk groups to 0. 4. pick one forwarding port per trunk group and turn the corresponding bit to 1. (each hash key may have different forwarding port, the rule to pick forwarding port is up to cpu.)
mds212 data sheet 63 zarlink semiconductor inc. 17.2.2 blocking multicast packets back to the source trunk for local multicast packets, the frame engine needs to bl ock the multicast packets from being sent to the same trunk group as the receiving (source) port. to do it, the search engine utilizes the trunk group id (tgid) in ecr1 register. the frame engine compares the tgid of the source and forwarding ports. if the two tgids are the same, the frame engine blocks the forwarding port for this multicast packet. the switch engine provides the tgid of the source port. example: the following demonstrates the port trun king scheme for multicast packet forwarding. 4 trunk group in a switch: group 0: port 0,1,2 in device 0 group 1: port 4, 5,6 in device 0 group 2: port 1, 2,3 in device 1 group 3: port 4, 5,6 in device 1 a multicast packet with vlan index=5 is received at port 0 of device 0. the membership of this vlan: device 0: port 0, 1, 2, 4, 5, 6, 7 device 1: port 1, 2, 3, 4, 5, 6, 8 hash key = 3 forwarding port for each group with hash key=3, port 2 for group 0 port 4 for group 1 port 3 for group 2 port 6 for group 3 figure 23 - multicast packet forwarding example 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0123456 ....... 11 7 a n d turn this port off since port 2 has the same tgid of source port 0 multicast packet received at port 0 of device 0 vlan idx=5, hash key=3 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0123456 ....... 11 7 device 0 local device 1 remote a n d forwarding port mask for key=3 vlan member index=5 forwarding ports for
mds212 data sheet 64 zarlink semiconductor inc. 17.3 mac address assignment in mds212, there are three ways to assign the mac address to each port. all the ports in the same device share the 44 msbs, mac[47:4], which are shown in adaor0 an d adaor1 registers, while the 4 lsbs, mac[3:0] are specified in adaor0 and adaor1 registers for port 0- port 7 and port 8-port 11, respectively. the 4 lsbs mac[3:0] can be assigned as follows: ? if the switch does not support port trunking, mac[3:0]= port number ? if the switch supports multiple mac addresses and port trunking, the ports in the same trunk group share the same mac[3:0]. the value of mac[3:0] is assigned by the trunk group (tg) table. ? if the switch supports only a single mac address, all the 4 lsbs of mac will be set the same value in ador0 and ador1 register 18.0 register definitions 18.1 register map all registers are grouped into sets: ? device configuration ? buffer memory interface ? frame control buffer ? queue management ? switching control ? link list management ? access control functions ? mac port control access control: w/r = these register bits may be read from and written to by software w/-- = these register bits may be written to by software, but not read. write only (--/r) = these register bits may be read but not written to by software. read only latched and held bits clear bits permanently set bits all registers are 32-bit wide. they are classified in the following tables: tag description address w/r 1. device configuration registers (dcr) gcr global control register 7c0 w/-- dcr0 device status register 7c0 --/r dcr1 signature & revision & id register 7c4 w/r dcr2 device configuration register 7c8 w/r table 9 - mds212 register map
mds212 data sheet 65 zarlink semiconductor inc. dcr3 interface status register 7cc --/r memp memory packed register 7dc w/r 2. interrupt controls isr interrupt status re gister-unmasked 7e0 --/r isrm interrupt status register-masked 7e4 --/r imsk interrupt mask register 7e8 w/r iar interrupt acknowledgment register 7ec w/-- 3. buffer memory interface mwars memory write addr. reg. - single cycle 780 w/-- mrars memory read addr. reg. - single cycle 784 w/-- mwarb memory burst write address register 788 w/-- mrarb memory burst read address register 78c w/-- mwdr memory write data register 790 w/-- mrdr memory read data register 794 --/r vtbp vlan id & mac member table base pointer 798 w/r mbcr multicast buffer control register 79c w/r rama ram block access register 7a0 w/r reserve must set to ?0x0001 0008? 7b8 w/r reserve must set to ?0x0001 0000? 7bc w/r 4. frame control buffers management fcbsl fcb stack size limit 740 w/r fcbst frame ctrl buffer stack - buffer low threshold 744 w/r bct buffer counter threshold 74c w/r bchl buffer counter hi-low selection 750 w/r 5. queue management cinq cpu input queue 708 w/-- cotq cpu output queue 70c --/r 6. switching control hpcr hisc processor control register 6c0 w/r hmcl0 hisc micro-code loading port-low 6c4 w/r hmcl1 hisc micro-code loading port-high 6c8 w/r hprc hisc priority control register 6d0 w/r mcs0r micro sequence 0 register 6d4 w/r mcs1r micro sequence 1 register 6d8 w/r tag description address w/r table 9 - mds212 register map (continued)
mds212 data sheet 66 zarlink semiconductor inc. fcr flooding control register 6dc w/r mcat mct aging timer 6e0 w/r tpmxr trunk port mapping table index register 6e4 w/-- tpmtd trunk port mapping table data register 6e8 w/r ptr pacing time regulation 6ec w/r mtcr mct threshold & co unter register 6f0 w/r 7. link list management lks link list status register 680 w/r ambx mail box access port 684 w/r afml free mail box list access port 688 w/r 8. access control function group 1 (chip level controls) avtc vlan type code 648 w/r axsc transmission scheduli ng control re gister 64c w/r attl transmission timing & threshold control register 650 w/r amiic mii command register 654 w/-- amiis mii status register 658 --/r afcria flow control ram input address 65c w/-- afcrid0 flow control ram input data 660 w/r afcrid1 flow control ram input data 664 w/r afcr flow control register 670 w/r amar0 multicast addr. for mac cont rol frames byte [3,2,1,0] 674 w/r amar1 multicast addr. for mac control frames byte [5,4] 678 w/r amct mac control frame type code register 67c w/r adar0 base mac address register - byte [3,2,1,0] 600 w/r adar1 base mac address register - byte [5,4] 604 w/r adaor0 mac offset address re gister port [0:7] 608 w/r adaor1 mac offset address register port [12:8] 60c w/r acktm timer for sof check 610 w/r afcoft10 flow control off time for 10mbps port 614 w/r afcoft100 flow control off time for 100mbps port 618 w/r afcht10 flow control holding time for 10mbps port 620 w/r afcht100 flow control holding time for 100mbps port 624 w/r 9. access control function group 2 (chip level controls) apmr port mirroring register 5c0 w/r tag description address w/r table 9 - mds212 register map (continued)
mds212 data sheet 67 zarlink semiconductor inc. pfr protocol filtering register 5c4 w/r thkm0 trunking forward port mask 0 (hash key=0) 5c8 w/r thkm1 trunking forward port mask 1 (hash key=1) 5cc w/r thkm2 trunking forward port mask 2 (hash key=2) 5d0 w/r thkm3 trunking forward port mask 3 (hash key=3) 5d4 w/r thkm4 trunking forward port mask 4 (hash key=4) 5d8 w/r thkm5 trunking forward port mask 5 (hash key=5) 5dc w/r thkm6 trunking forward port mask 6 (hash key=6) 5e0 w/r thkm7 trunking forward port mask 7 (hash key=7) 5e4 w/r ipmcas0 ip multicast mac address signature low register - byte [3:0] 5e8 w/r ipmcas1 ip multicast mac address signature high register - byte [5:4] 5ec w/r ipmcmsk0 ip multicast mac address mask low register - byte [3:0] 5f0 w/r ipmcmsk1 ip multicast mac address mask high register - byte [5:4] 5f4 w/r cfcbhdl fcb handle register for cpu 580 --/r cpuircmd cpu internal ram command register 584 w/r cpuirdat0 cpu internal ram data register - 0 588 w/r cpuirdat1 cpu internal ram data register - 1 58c w/r cpuirdat2 cpu internal ram data register - 2 590 w/r cpuirrdy internal ram read ready for cpu 594 --/r ledr led register 598 w/r 10. ethernet mac port control registers - (substitute [n] with port number, n={0.11} ecr0 mac port control register [n*4]0 w/r ecr1 mac port configuration register [n*4]4 w/r ecr2 mac port interrupt mask register [n*4]8 w/r ecr3 mac port interrupt status register [n*4]c --/r ecr4 status counter wrap signal [n*4+1]0 w/r pvidr pvid register [n*4+2]4 w/r tag description address w/r table 9 - mds212 register map (continued)
mds212 data sheet 68 zarlink semiconductor inc. 18.2 register definitions 18.2.1 device configuration register 18.2.1.1 gcr - global control register ? access: zero-wait-state, direct access, write only ? address: h7c0 bit [2:0]op-code 3-bit operation control code bit [7:4] syn bits, reserved for hisc usage. 18.2.1.2 dcr0 - device status register ? access: zero-wait-state, direct access, read only ? address: h7c0 bit [1:0] status 2-bit device operation status code ? power-up default = 00 bit [31:2] reserved 31 24 23 20 19 16 15 12 11 8 7 4 3 2 0 sync op-code op-code command description 000 clr rst clear device reset: allows state machines to exit from reset state and to initialize their internal control parameters if necessary. 001 reset device reset: resets all internal state machines of each device and stays in reset state (except the processor bus interface logic). 010 exec execution: allows state machines to start their normal operations. 011 -- no-op 1xx -- no-op table 10 - global control register 31 8765432 0 status status state description 00 init initialization: device is in idle state pending for system software initialization. 01 reset device reset: device is in reset state. 10 exec execution: device is under normal operation. table 11 - device status register
mds212 data sheet 69 zarlink semiconductor inc. 18.2.1.3 dcr1 - signature, revision & id register ? access: non-zero-wait-state, direct access,write/read ? address: h7c4 bit [3:0] device revision code bit [6:4] reserved bit [15:8] signature 8-bit device signature bit [19:16] reserved bit [24:20] dev_id 5-bit device id (read/write) bit [31:25] reserved 18.2.1.4 dcr2 - device configuration register ? access: non-zero-wait-state, direct access, write/read ? address: h7c8 bit [1:0] sc system clock rate default = 00 00= 100mhz 10=90mhz 01 = 120mhz 11=80mhz bit [2] ip irq output polarity control power-up default =0 0 = active low output 1 = active high output bit [3] sm system configuration mode 0=nonblocking (for mds212, always equal to 0) 1=blocking sram memory characteristics bit [4] ml buffer memory level, which can be either 2 chips or 4 chips. 0 = 2 memory chips default = 0 1 = 4 memory chips bit [6:5] mt memory chip type default = 01 00 = 64k x 32-bit 01 = 128k x 32-bit 10 = 256k x 32-bit 11 = 512k x 32-bit bit [8:7] reserved 31 25 24 20 19 16 15 12 11 8 7 4 3 2 0 dev_id signature rev 31 27 26 25 22 21 20 19 18 17 9 8 7 6 5 4 3 2 0 1 boot strap ip mc fe and mac se configuration mt ml sm ip sc
mds212 data sheet 70 zarlink semiconductor inc. search engine configuration bit [9] se_agen aging enable, if which is true, the old mct can be aged out. default = 1 0 = disable aging 1 = enable aging bit [11:10] hm hashing mode, each of which uses different bits of mac address to come up with each bit of hashing key. default = 00 00=mode 0 01=mode 1 10=mode 2 11=mode 3 bit [13:12] hs hashing size default = 01 00= 8 01= 9 10= 10 11= tdb bit [14] vsw lan aware switch default = 0 0 = vlan unaware 1 = vlan aware bit [15] noipm no ip multicast default = 1 1 = ip multicast disable 0 =ip multicast enable bit [16] gln global learning disable, where cpu shall disable global learning before look into it as a whole piece. default = 0 1 = learning disable 0 = learning enable bit [17] partial syn enable partial synchronization enable for mac table default=0 0= fully synchronization for mct table 1= partial synchronization for mct table bit [18] reserved
mds212 data sheet 71 zarlink semiconductor inc. frame engine and mac configuration boot strap determine by the bootstrap value. bit [19] fe_agen aging enable. if true, the memory resources, occupied by the old message, will free up. default = 1 0 = disable aging 1 = enable aging bit [20] fof forward oversize framespower-up default =0 0 = discard oversize frames 1 = forward oversize frames bit [21] dec_buffer_c nt decrements buffer counter. when the software writes ?1? to this bit, the frame engine decreases buffer counter by one. bit [22] bc_en buffer counter enable 0 = disable (no head of line control) 1 = enable bit [23] sta_en status counter enable 0 = collect status in counter disable1 = collect status in counter enable bit [24] sel_pcs default=0 0 = use external pcs 1 = use internal pcs in the chip bit [25] link_gt tx led will be off when the link is down and this bit is 0 default =0 0 = gate 0ff tx_en when link down 1 = not gate off tx_en when link down bit [26] ipmcip multicast privileges enable: ip multicast traffic has a privilege over regular multicast traffic. default=0 0= disable 1= enable bit [27] bmod control bus mode (read only bit) must be 0 bit [28] rw cpu read/write control polarity selection (read only bit) 0 = r/w# 1 = w/r# bit [29] swm switching mode (read only bit) default=1 0 = managed mode 1 = unmanaged mode
mds212 data sheet 72 zarlink semiconductor inc. 18.2.1.5 dcr3 - interfaces status register ? access: zero-wait-state, di rect access, read only ? address: h7cc bit [3:0] reserved bit [7:4] mem_stat buffer memory interface status bit [4] bb buffer memory busy, cpu interface is busy accessing memory bit [5] re read fifo empty, the fifo that cpu interface reads is empty bit [6] we write fifo empty, the fifo that cpu writes is empty bit [7] res. reserved bit [11:8] que_stat queue manager interface status bit [8] iq_rdy cpu input queue is re ady for cpu to write into queue bit [9] iq_full cpu input queue is full bit [31:12] reserved 18.2.1.6 memp - memory packed register ? access: non-zero-wait-state, direct access, write/read ? address: h7dc bit [7:0] rcl read cycl e limit (unit is syst em clock). default=16 threshold of re ads cycle time. bit [15:8] wcl write cycle li mit (unit is system clock). threshold of writes cycle time. default=16 bit [16] np not packed default=0 np=0 enable the feature of memory read/write packed. np=1 disable, memory access will be a pure round-robin scheme. bit [31:17] reserved bit [30] psd master device enable (read only bit) default=1 1 =primary 0 = secondary bit [31] mrdy option of merge the rdy and b_rdy as one pin (read only bit) default=1 0 = merged pin 1 = separated pins 31 25 24 21 20 16 15 12 11 8 7 4 3 2 0 1 que_stat mem_stat 31 30 17 16 15 8 7 5 0 np wcl rcl
mds212 data sheet 73 zarlink semiconductor inc. 18.2.2 interrupt control registers ? four 32-bit control registers. ? isr interrupt status register identify the unmasked interrupt request sources ? access: zero-wait-state, direct access, read only ? address: h7e0 ? isrm masked interrupt status reg. identif y the sources of interrupt with masking ? access: zero-wait-state, direct access,read only ?address: h7e4 ? imsk interrupt mask register define s the interrupt sources to be masked ? access: non-zero-wait-state , direct access,write/read ? set bits to 1 to mask the corresponding interrupt sources ?address: h7e8 ? iar interrupt acknowledgment reg. clear the interrupt request bits ? access: non-zero-wait-state, direct access,write only ? set bits to 1 to clear the corresponding interrupt sources ?address: h7ec all 4 registers have a common register format and bit assignment interrupt mac port mapping bit/port interru pt source interrupt sources (the following bits need to be redefined.) bit [0] cpu_q_out cpu output queue level interrupt bit [1] bsr bad switch response bit [2] double r double release bit [3] fcb_low fcb low bit [4] hisc_bp hisc instruction pointer matched with breakpoint register bit [5] reserved bit [6] reserved bit [7] mail_arr mail arrived from hisc bit [8] hisc_to hisc timeout interrupt bit [9] reserved bit [10] fml_av link manager informs cpu that at least 16 free mail entry available after cpu encounters empty free mail list situation. bit [23:11] mac_port interrupt from mac ports bit [11] for port 0, bit [12] fo r port 1 ? bit [23] for port 12. bit [24] mct search engine found looped mct chain. bit [31:25] reserved note: mail_arr, cpu_q_out, and interrupts cannot be cleare d by the cpu. they will be cleared whenever their queues are emptied. 31 25 24 23 11 10 9 8 7 6 5 4 3 2 1 0 mct mac_port interrupt fml mail bp fcbl dbr bsr cpq
mds212 data sheet 74 zarlink semiconductor inc. 18.2.3 buffer memory interface register 18.2.3.1 mwars - memory write address register - single cycle ? access: zero-wait-state, via fifo, write ? address: h780 bit [0] lk lock flag (for internal memory only) lk=0 unlocklk=1 lock bit [1] sp swap byte order bit [20:2] ma [20:2] buffer memory address bit [20:2] ? (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicates the address is internal or external memory i/e=0 internal memory i/e=1 external memory bit [27:23] count must be 00001 bit [31:28] be [3:0] byte lane enables 31 28 27 26 24 23 22 21 20 3 2 1 0 be[3:0] 00001 i/e address ma[20:3] sp lk cpu bus type bit [31] bit [30] bit [29] bit [28] little endian be [3] be [2] be [1] be [0] big endian be [0] be [1] be [2] be [3]
mds212 data sheet 75 zarlink semiconductor inc. 18.2.3.2 mrars - memory read address register - single cycle access: zero-wait-state,via fifo,write address:h784 bit [0] lk lock flag memory lk=0 unlock lk=1 lock bit [1] sp swap byte order bit [20:2] ma [20:2] buffer memory address bit [20:2] ? (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicate the address is internal or external memory i/e=0 internal memory i/e=1 external memory bit [27:23] count must be 00001 bit [31:28] be [3:0] byte lane enables. 18.2.3.3 address registers for burst cycle ? two 32-bit burst size regi sters share a common format ? mwarb memory address register ? burst writ e (in d-words) ? maximum 8 d-words ?address: h788 ? mrarb memory address register ? burst re ad (in d-words) ? maximum 8 d-words ?address: h78c ? access: zero-wait-state, via fifo, write bit [0] lk lock flag lk=0 unlock lk=1 lock bit [1] sp swap byte order bit [2] reserved bit [20:2] ma [20:2] buffer memory ad dress bit [20:2] ? (bit [1:0] = 00) bit [21] reserved bit [22] i/e indicate the address is internal or external memory i/e=0 internal memory i/e=1 external memory 31 28 27 24 23 22 21 20 3 2 1 0 be[3:0] 0001 i/e address ma[20:2] sp lk 31 28 27 24 23 22 21 20 3 2 1 0 count i/e address ma[20:2] sp lk
mds212 data sheet 76 zarlink semiconductor inc. bit [27:23] count count = burst size in double words burst size for internal memory is up to 8 d-words. burst size for external memory is up to 16 d-words 00001 = 1 d-word, ??01000 = 8 d-word 01111 = 15 d-word 10000 = 16 d-word valid value range for inter nal memory is {1 to 8} valid value range for extern al memory is {1 to 16} caution: when setting count = 16, the starting address has to be in the q-word boundary. that is ma[2]=0. bit [31:28]reserved 18.2.3.4 memory read/write data registers ? four 32-bit data registers share a common format ? mwdr memory write data register ? access: zero-wait-state, via fifo, write only ? address: h790 ? mrdr memory read data register ? access: zero-wait-state, direct access, read only ? address: h794 ? byte order depends on cpu types ? little endian cpus ? big endian cpus 18.2.3.5 vtb - vlan id table base pointer ? access: non-zero-wait-stat e, direct access, write/read ? address: h798 bit [5:0] vidb vlan id tabl e base, serves as [20:15] bits of address. (vlan id table is 32kb) bit [6] reserved bit [8:7] vlms the size of vlan mac table default=11 00= reserved 10=32k (for 128 vlans) 01=16k (for 64 vlans) 11=64k (for 256 vlans) 31 24 23 16 15 8 7 0 byte[3] byte[2] byte[1] byte[0] 31 24 23 16 15 8 7 0 byte[0] byte[1] byte[2] byte[3] 31 17 16 15 11 10 9 8 7 6 5 0 vmacb vlms vlan id base
mds212 data sheet 77 zarlink semiconductor inc. bit [15:9] vmacb vlan mac table base, serves as [20:14] bit of address. this table indicates the association of mac address and vlan. bit [31:16] reserved 18.2.3.6 mbcr - multi cast buffer control register ? access: non-zero-wait-state, direct access, write/read ? address: h79c bit [4:0] max_mc_fd maximum number of multicast frames allowed for forwarding. bit [10:5] rmc_buf_rsv number of buffers reserved for receivin g remote multicast frames. bit [19:11] max_cnt_lmt maximum number of multicast frames allowed per device bit [21:20] mcfth multicast forwarding threshold: watermark for forwarding ff to drop regular multicast packet if ipmc bit in dcr2[26] is on. cpu can set four level watermarks, which are programmable. 00=25% 10=75% 01=50% 11=100% bit [31:22] reserved 18.2.3.7 rama - ram counter block access register ? access: non-zero-wait-state, direct access, write/read ? address: h7a0 ? ram counter block contains 12 counte r blocks (one for each port) port 0 co unter block starts at address 0.) the size of each block is 16 double words, which holds, in total, 30 statistic counters. the size and type of each counter is referred to the register ecr4. ? cpu uses this regist er to access the specified statistic counter by setting the start address of ram counter block and the length. bit [3:0] bst_cnt read /write burst (length) of ram block. (unit = 1double words) bit [10:4] st_adr read/write start address. bit [14:11] reserved bit [15] w/r ram block access write/read indicator 1 = write 0 = read bit [16:31] reserved note: the access range is equal to from st_adr to end_adr= s_ adr+ bst_cnt.the end_adr cannot cross the boundary of each port block, i.e., 8 double words. 31 22 21 20 19 11 10 5 4 0 mcth max_cnt_lmt rmc_buf_rsv max_mc_fd 31 16 15 14 11 10 4 3 0 w/r st_adr bst_cnt
mds212 data sheet 78 zarlink semiconductor inc. 18.2.3.8 reserve register 1 ? access non-zero-wait-state direct-access write/read ? address: h7b8 must be set to ?0x00010008? 18.2.3.9 reserve register 2 ? access non-zero-wait-state direct-access write/read ? address: h7bc must be set to ?0x00010000? 18.2.4 frame control buffers management register 18.2.4.1 fcbsl - fcb queue ? access: non-zero-wait-state, direct access, write/read ? address: h740 bit [10:0] defines max # of fcb buffers size range: 1 entry, to 1024 entries bit [17:11] aging timer base defines the time interval between scanning of fcb buffers for aged buffers aging time = (number of valid fcb buffers* aging timer base) msec 18.2.4.2 fcbst - fcb queue - buffer low threshold ? access: non-zero-wait-state, direct access, write/read ? address: h744 bit [5:0] buf_low_th buffer low threshold ? the number of frame control buffer handles left in the queue to be considered as running low and trigger the interrupt to the cpu. bit [31:6] reserved 31 16 15 0 0x0001 0x0008 31 25 16 15 0 0x0001 0x0000 31 18 17 16 11 10 9 0 aging timer base max # pf fcb buffer 31 23 16 15 11 7 6 5 0 blowth
mds212 data sheet 79 zarlink semiconductor inc. 18.2.4.3 bct - (fcb) buffer counter threshold ? access non-zero-wait-state direct-access write/read ? address: h74c bit[9:0] low_limit low limit number of frames to each destination port (i.e., source port limits the # of fcb used by each destination port) bit[19:10 hi_limit high limit number of frames to each destination port (i.e., source port limits the # of fcb used by each destination port) 18.2.4.4 bchl - buffer counter hi-low selection ? access non-zero-wait-state direct-access write/read ? address: h750 bit[11:0] lp_hi_low sel selection for low or high limit of buffer counter for local device 12 bits maps to 12 ports in local device 1 = select hi limit 0 = select low limit bit[12] reserved bit[24:13] rp_hi_low sel selection for low or high limit of buffer counter for remote device 13 bits maps to 13 ports in remote device 1 = select hi limit 0 = select low limit bit[31:25] reserved 18.2.5 queue management register 18.2.5.1 cinq - cpu input queue ? access: non-zero-wait-state, direct access, write only ? address: h708 note: check iq_rdy=1 in dcr3 (interface status register) before writing into cpu input queue. 18.2.5.2 cotq - cpu output queue ? access: non-zero-wait-stat e, direct access, read only ? address: h70c bit [30:0] 31-bit cpu output queue entry bit [31] status queue is ready 31 19 10 9 0 hi limit low limit 31 25 24 13 12 11 0 rp_hi_low sel lp_hi_low sel 31 0 32-bit data from cpu input queue 31 30 0 cpu output queue entry
mds212 data sheet 80 zarlink semiconductor inc. 18.2.6 switching control register 18.2.6.1 hpcr - hisc processor control register ? access: non-zero-wait-state, direct access, write/read ? address: h6c0 bit [0] ht halt the hisc processo r from execution not apply for non-managed mode (it can be fixed in next cut.) power-up default = 1 bit [1] ld switch the micro-code memory from instruction fetch mode to down-loading mode bit [2] rs reset ip to 0 ? (write only bit) (this bit is auto reset to 0 after ip is reset to 0) bit [31:3] reserved 18.2.6.2 hmcl0 - hisc micro-code loading port ? low ? access: non-zero-wait-state, direct access, write/read ? address: h6c4 ? loading micro code into hisc. bit [31:0] hisc hisc instruction word has total 40 bit-wide. needs to be instruction broken into two registers. word [31:0] 31 3210 rs ld ht rs ld ht state description 101 init initialization state: stopped hisc execution, reset ip to 0. 001 halt halt state: stopped hisc execution, waiting for ht=0 01x load micro-code loading state: stopped hisc execution, increment ip for every wr/rd to hmpc. 100 start start state: reset ip=0, and start hisc execution. 000 exec execution state: continue hisc execution without reset ip. 11x -- illegal state table 12 - hpcr - hisc processor control register 31 19 0 hisc instruction word [31:0]
mds212 data sheet 81 zarlink semiconductor inc. 18.2.6.3 hmcl1 - hisc micro-code loading port ? high ? access: non-zero-wait-state, direct access, write/read ? address: h6c8 bit [7:0] hisc instruction word [39:32] bit [31:8] reserved 18.2.6.4 ms0r micro sequence 0 register ? access: zero-wait-state, di rect access, write/read ? address: h6d4 bit[31:0] databit [31:0] data bit [31:0] to the sequencer ram (the length of micro sequence data is 54-bit, need to be broken into tow registers) 18.2.6.5 ms1r micro sequence 1 register ? access: zero-wait-state, di rect access, write/read ? address: h6d8 31 87 0 hisc instruction [39:32] 31 24 23 16 15 8 7 0 databit[31:0] 31 29 28 24 23 22 21 20 19 16 15 8 7 0 cnt databit [51:32] bit [19:0] data bit [51:32] to the sequencer ram bit [31:29] 000 001 010 011 100 101 110 cnt control bits (write only bits) nop load restart ptr incadr halt unload unhalt bit [28:20] reserved
mds212 data sheet 82 zarlink semiconductor inc. 18.2.6.6 flooding control register ? access: non-zero-wait-state, direct access, write/read ? address: h6dc bit [7:0] m2cr multica st to cpu rate restricts the number of frames within the time window defined in bit[15:12] bit [11:8] u2mr unicast to multicast rate restricts the number of flooding unicast frames within the time window bit [14:12] time base defines the time window used by m2cr and u2mr 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 100us bit [23:15] u2cr unicast to cpu rate restricts the number of frames within the time window defined in bit[15:12] bit [31:24] reserved 18.2.6.7 mcat - mct aging timer ? access: non-zero-wait-state, direct access, write/read ? address: h6e0 bit [19:0] when the value is reached, it ages out default=0 msec (unit=msec) must be configured to not zero value. suggestion value: 5msec. 18.2.6.8 tpmxr - trunk port mapping table index register ? access: non-zero-wait-state, direct access, write/read ? address: h6e4 ? for trunk port mapping table pointer bit [7:0] 8-bit table entry index bit [8:31] reserved value set to 0 31 24 23 16 15 14 12 11 8 7 0 unicast to cpu rate time base u2mr multicast to cpu rate 31 20 19 0 mct aging timer 31 87 0 entry index
mds212 data sheet 83 zarlink semiconductor inc. 18.2.6.9 tpmtd - trunking port mapping table data register ? access: non-zero-wait-state, direct access, write/read ? address: h6e8 bit [0:3] port id trunking port bit [4] dv device id 18.2.6.10 ptr - pacing time regulation ? access non-zero-wait-state direct-access write/read ? address: h6ec ? use for pacing traf fic to remote ports via xpressflow pipe or local transmission bit [3:0] 100_tm 100m po rt timer default =5 bit [7:4] rsvd bit [11:8] mc_tm multicast timer default =5 bit[15:12] uc_tm unicast timer default =5 unit time = 80 nsec.(for 64bytes frame.) note that the frame engine determines the tic value de pendent upon the frame. if short frame, it takes above value. for long frame (> 64 frame), it will double the above value as the reference. 18.2.6.11 mtcr - mct threshold & counter register ? access: non-zero-wait-state, direct access, write/read ? address: h6f0 bit [10:0] reserved bit [21:11] mct threshold alert system when free mct entries are below this threshold 18.2.7 link list management 18.2.7.1 lks - link list status register ? access: zero-wait-state, direct access, read only ? address: h680 bit [0] mail box is not ready for cpu to send entry to hisc 1=not ready 0=ready 31 43 0 dv port id 31 15 12 11 8 7 4 3 0 uc_tm mc_tm 100_tm 31 22 21 11 10 0 mct threshold 31 43 2 1 0
mds212 data sheet 84 zarlink semiconductor inc. bit [1] free mail box is not re ady for cpu to put entry into 1= not ready 0=ready bit [2] cpu gets mail from hisc 1= ready 0=not ready bit [3] free mail box ha s entry for cpu to get 1=ready 0=not ready bit [31:4] reserved 18.2.7.2 ambx - mail box access port ? access: zero-wait-state, di rect access, write/read ? address: h684 ? in write mode, cpu sends mail to hisc ? in read mode, cpu receives mail from hisc bit [20:0] entry handle, t he bit [2:0] always 2?b000 bit [29:21] reserved bit [30] link list is empty. ( read only ) bit [31] link list is ready. (s ame as bit [0] of lks register) ( read only ) 18.2.7.3 afml - free mail box list access port ? access: zero-wait-state, di rect access, write/read ? address: h688 bit [20:0] entry handle, t he bit [2:0] always 2?b000 bit [29:21] reserved bit [30] link list is empty. ( read only ) bit [31] link list is ready. (same as bit [1] of lks register) ( read only ) 18.2.8 access control function 18.2.8.1 avtc - vlan type code register ? access: non-zero-wait-state, direct access, write/read ? address: h648 31 30 21 20 01 0 entry handle 0 0 0 31 30 20 0 1 entry handle 0 0 0 31 24 23 16 15 8 7 0 p7 p6 p5 p4 p3 p2 p1 p0 vlan type code
mds212 data sheet 85 zarlink semiconductor inc. bit [0:15] 2-byte vlan type code defined by ieee 802.1q vlan standard bit [31:16] priority 4 level priority denoting by 2-bit for each mapping 8 level vlan priorities to 4 level intern al priorities. 18.2.8.2 axsc - transmission scheduling control register ? access: non-zero-wait-state, direct access, write/read ? address: h64c bit [11:0] qsw[2:0] transmission queue service weight for queue 2, 1, & 0. (4 bit each) defines the servic e rate for each queue qr0-qr3 qr0 : qr1 : qr2 : qr3 qr0 = qsw0*(qsw1+1)* (qsw2+1) qr1 = qsw1*(qsw2+1) qr2 = qsw2 qr3 = 1 note: queue 0 has the highest priority. queue size is defined in the queue control table. 18.2.8.3 attl - transmission timing control ? access: non-zero-wait-state, direct access, write/read ? address: h650 bit [4:0] transmission que ue aging time out counter bit[13:5] frame latest departure time bit [21:14] txfifot transmission fifo threshold in bytes (default =0) unit=8bytes 0= cut through at the destination 100m port when the value does not equal zero, it indicates the port cannot start sending frames out, until the txfifo reaches the threshold or eof. 18.2.9 mii serial management channel these registers are part of the management module. they allow the upper layer services to communicate with any one of the phys that are connected to the management module through the serial interface. 31 12 11 8 7 4 3 0 qsw2 qsw1 qsw0 31 24 22 21 14 13 5 4 0 txfifo threshold[7:0] depart_time qmt_cnt
mds212 data sheet 86 zarlink semiconductor inc. 18.2.9.1 amiic - mii command register this is a write-only register. the upper layer services writ e the management frame to be sent to the phys into this register. the msb (bit 31) is the first bit sent over the serial interface. ? access: non-zero-wait-state, direct access, write only ? address: h654 bit [31:30] st start of frame ? always = ?01? bit [29:28] op operation code ? ?10? for read command and ?01? for write command bit [27:23] phy_ad 5-bit phy address bit [22:18] reg_ad 5-bit register address in phy bit [17:16] ta turnaround ? ?10? for write bit [15:0] data 16-bit write data to phy 18.2.9.2 amiis - mii status register the upper layer services should read this register fo r data sent by the phys. the lower 16 bits contain data received by the management module ? access: non-zero-wait-stat e, direct access, read only ? address: h658 bit [31] rdy data ready bit [30] valid data valid bit [15:0] data 16-bit read data from phy 31 30 20 28 27 23 22 18 17 16 15 2 1 0 st op phy_ad reg_ad ta data (16-bit) 31 30 29 16 15 2 1 0 ry vd data (16-bit) bit [31] rdy bit [30] valid description 1 1 data field contains valid data from the phys. 1 0 data field contains invalid data from the phys. 0 x data field is not ready to be read by switch manager cpu. table 13 - amiis - mii status register
mds212 data sheet 87 zarlink semiconductor inc. 18.2.10 flow control management 18.2.10.1 afcria - flow control ram input address access: non-zero-wait-state, direct access, write only address: h65c bit [2:0] 3-bit address for the ram in mac storing flow control frame usage: flow control frame consists of 64 bytes. usin g afcria and afcrid0-1, the cpu loads 8 bytes each time. the cpu specifies the address in afcria and writ es the content of 4 bytes in afcrid0 and 4 bytes in afcrid1. then repeats the above procedure 8 times to load a whole flow control frame into the chip. 18.2.10.2 afcrid0 - flow control ram input data 0 ? access: non-zero-wait-state, direct access, write only ? address: h660 bit [31:0] content of flow control frame [31:0], flow control frame has 64 bytes and is defined by ieee 18.2.10.3 afcrid1 - flow control ram input data 1 ? access: non-zero-wait-state, direct access, write only ? address: h664 bit [31:0] content of fl ow control frame [63:32] 18.2.10.4 afcr - flow control register ? access: non-zero-wait-state, direct access, write/read ? address: h670 bit [9:0] reserved bit [12:10] xon_thd defines the minimum # of free frame buffers before transmitting xon flow control frame. 31 32 0 address 31 24 23 16 15 8 7 0 content of input flow control frame[31:0] 31 24 23 16 15 8 7 0 content of input flow control frame[63:32] 31 16 15 14 13 12 10 9 0 xn fe ae xon_thd
mds212 data sheet 88 zarlink semiconductor inc. bit [13] queue aging enable tx queue aging function enable bit [14] flush enable when stack is full, enable flush procession 0 = disable 1 = enable bit [15] xon enable full duplex xon enable 0 = disable 1 = enable bit [31:16] reserved 18.2.10.5 amar[1:0] - multicast address reg. for mac control frames ? this 6-byte mac address is stored in two 32-bit registers ? amar0 mac address byte [3:0] ? address: h674 ? amar1 mac address byte [5:4] ? address: h678 ? access: non-zero-wait-state, direct access, write/read 18.2.10.6 amct - mac control frame type code register access: non-zero-wait-state , direct access, write/read address: h67c ? 2-byte mac control frame type code defined by i eee 802.3x full duplex flow control standard 18.2.10.7 adar [1:0] - base mac address registers ? the 6-byte mac address is stored in two 32-bit registers ? adar0 mac address byte [3:0] ?address: h600 ? adar1 mac address byte [5:4] ?address: h604 ? access: non-zero-wait-state, direct access, write/read ? these two registers define the base mac address of the device. ? bit [3:0] of byte 0 (mac5) is always set to 0. ? mac address for each port is defined by 31 24 23 16 15 8 7 0 amar0 mac 3 mac 2 mac 1 mac 0 amar1 mac 5 mac 4 31 24 23 16 15 8 7 0 frame type 31 24 23 16 15 8 7 0 adar0 mac 3 mac 2 mac 1 mac 0 adar1 mac5 mac 4 xon thd offreefcb _ min.# = ? ? ? ? ? ? 8
mds212 data sheet 89 zarlink semiconductor inc. ? mac address for port n = base mac ad dress + mac offset [n] where n = {0..12} ? mac offset[n] is defined by the following registers 18.2.10.8 adaor0 - mac offset address register 0 ? mac offset address for po rt [7:0], 4-bit per port ? access: non-zero-wait-state, direct access, write/read ? address: h608 bit [3:0] mac offset address for port 0 bit [7:4] mac offset address for port 1 bit [11:8] mac offset address for port 2 bit [15:12] mac offset address for port 3 bit [19:16] mac offset address for port 4 bit [23:20] mac offset address for port 5 bit [27:24] mac offset address for port 6 bit [31:28] mac offset address for port 7 usage: there are three ways to assign the mac address to each port. all ports in the same device share the 44 msbs, mac[47:4] in adar [0:1], while the 4 lsbs, mac offset [3:0] can be assigned as follows: 18.2.10.9 adaor1 - mac offset address register 1 ? mac offset address for po rt [12:8], 4-bit per port ? access: non-zero-wait-state, direct access, write/read ? address: h60c bit [3:0] mac offset address for port 8 bit [7:4] mac offset address for port 9 bit [11:8] mac offset address for port 10 bit [15:12] mac offset address for port 11 bit [31:16] reserved 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 port7_offset port6_offset port5_offset port4_offset p ort3_offset port2_offset port1_offset port0_offset 1. in a managed system, if the device does not support port trunking, mac_offset[3:0]= the port number. 2. in a managed system where device supports port tr unking, the ports in the same trunk group shares the same ma c[3:0]. the value of mac[3:0] is assigned by the smallest port number in the trunk group. 3. in a managed system, if bit [18] of dcr2, smac=0, all ports are assigned to a single mac. 4. in an unmanaged system, ma c[3:0] is fixed for all devices (i.e., only one mac[3:0] address fo r the whole system). 31 16 15 12 11 8 7 4 3 0 port11_offset port10_offset port9_offset port8_offset
mds212 data sheet 90 zarlink semiconductor inc. 18.2.10.10 acktm - timer for sof checking ? access: non-zero-wait-state, direct access, write/read ? address: h610 bit [9:0] xoff_cktm the time out value to check sof after xoff bit [31:10] reserved 18.2.10.11 afcht10 - flow control hold time of 10mbps port ? access: non-zero-wait-state, direct access, write/read ? address: h620 bit [15:0] hbk_tm_10 holding time to remote station for head of line blocking control for 10m port. bit [31:16] reserved 18.2.10.12 afcht 100 - flow control hold time of 100mbps port ? access: non-zero-wait-state, direct access, write/read ? address: h624 bit [15:0] hbk_tm_100 holding time to remote station for head of line blocking control for 100m port. bit [31:16] reserved 18.2.10.13 afcoft10 - flow c ontrol off time of 10mbps port access: non-zero-wait-state, direct access write/read address: h614 bit [15:0] fl_off_10m off time to remote station for 10m port. bit [31:16] reserved 31 10 9 0 xoff_cktm 31 16 15 0 hbk_tm_10 31 16 15 0 hbk_tm_100 31 24 23 16 15 0 fl_off_10m
mds212 data sheet 91 zarlink semiconductor inc. 18.2.10.14 afcoft100 - flow control off time of 100mbps port ? access: non-zero-wait-state, direct access, write/read ? address: h618 bit [15:0] fl_off_100m off time to remote station for 100m port. bit [31:16] reserved 18.2.11 access control function group 2 (chip level) 18.2.11.1 apmr - port mirroring register ? access: non-zero-wait-state, direct access, write/read ? address: h5c0 bit [11:0] mirr_port the 10/100 port chosen to be mirrored bit [12] local/remote in dicates the mirrored port is from a local or remote device. 0=local 1=remote bit [13] rx/tx indicates wh ether the mirror is receiv ing data or transmitting data bit [14] mp0 mirror to port 0 default=0) mp0=1 mirror to port 0 mp0=0 mirror not go to port 0 bit [31:15] reserved 18.2.11.2 pfr - protocol filtering register ? access: non-zero-wait-state, direct access, write/read ? address: h5c4 the search engine will provide ingress filtering on a per-port basis. each bit of pf register (default value = 0) will cause packets matching that category to be dropped. bit [7:0] protocol filt er for unicast frames bit [0] ip ? ethernet ii encapsulation bit [1] ip ? 802_snap encapsulation bit [2] ipx ? etherne t ii encapsulation bit [3] ipx ? 802_snap encapsulation bit [4] ipx ? 802.2 encapsulation bit [5] ipx ? 802.3_raw encapsulation bit [6] other (packets with unknown encapsulation, or non-ip, non-ipx packets) 31 24 23 16 15 0 fl_off_100m 31 15 14 13 12 11 0 mpo rx/tx l/r mirror port 31 1615 8765432 1 0
mds212 data sheet 92 zarlink semiconductor inc. bit [7] untagged frames bit [15:8] protocol filter for multicast frames bit [8] multicast ip ? et hernet ii encapsulation bit [9] multicast ip ? 802_snap encapsulation bit [10] multicast ipx ? ethernet ii encapsulation bit [11] multicast ipx ? 802_snap encapsulation bit [12] multicast ipx ? 802.2 encapsulation bit [13] multicast ipx ? 802.3_raw encapsulation bit [14] multicast other (packets with unknown encapsulation, or non-ip, non-ipx packets) bit [15] multicast untagged frames bit [31:16] reserved usage: there is only one pfr register. for each port there is an enable bit (ecr1 bit 6: ife- ingress filter enable) which determines whether the settings in pfr are applied to that port. 18.2.11.3 thkm [0:7] - trunking forwarding port mask 0-7 ? eight trunking hash key mask registers shared the same format. ? thkm0 trunking forwarding po rt mask for hash key 0 ? address: h5c8 ? thkm1 trunking forwarding po rt mask for hash key 1 ? address: h5cc ? thkm2 trunking forwarding po rt mask for hash key 2 ? address: h5d0 ? thkm3 trunking forwarding po rt mask for hash key 3 ? address: h5d4 ? thkm4 trunking forwarding po rt mask for hash key 4 ? address: h5d8 ? thkm5 trunking forwarding po rt mask for hash key 5 ? address: h5dc ? thkm6 trunking forwarding po rt mask for hash key 6 ? address: h5e0 ? thkm7 trunking forwarding po rt mask for hash key 7 ? address: h5e4 ? access: non-zero-wait-state, direct access, write/read bit [11:0] tk_msk port trunk mask for trunking hash key bit [31:12] reserved cpu sets up this table as follows: 1. set all bits not in trunk groups to 1 2. set all bits in the trunk group to 0 3. pick one forwarding port per trunk group and turn the corresponding bit to 1 (each hash key may have different forwarding ports, the rule to pick forwarding ports is up to the cpu). 31 12 11 0 tk_msk
mds212 data sheet 93 zarlink semiconductor inc. usage : these masks are used to prevent flooded or multic ast packets from being transmitted out with more than one port on a trunk. the trunking hash key is used to select the proper mask (for load distribution). the mask value will be set up to mask off all but one port within each trunk group. 18.2.11.4 ipmcas - ip multicast mac address signature usage: for following four registers ipmcas0, ipmcas1, ipmcmsk0 and ipmcmsk1, are used to distinguish between ip multicast traffic and regular multicast. th e mac for ip multicast are h?01:00:5e:00:00:00? to h? 01:00:5e:7 f:ff:ff? and the mask for ipmc is: h?ff:ff:ff:80:00:00?. ? the 6-byte of ip multicast mac address is stored in two 32-bit registers ? ipmcas0 ip multicast ma c address byte [3:0] ? address: h5e8 ? ipmcas1 ip multicast ma c address byte [5:4] ? address: h5ec ? access: non-zero-wait-state, direct access, write/read ? these two registers define the mac address signature of ip multicast. ? default = h? 01:00:5e:7f:ff:ff? 18.2.11.5 ipmcmsk - ip multicast mac address mask ? the 6-byte of ip multicast mac mask is stored in two 32-bit registers ? ipmcas0 ip multicast mac mask byte [3:0] ? address: h5f0 ? ipmcas1 ip multicast mac mask byte [5:4] ? address: h5f4 ? access: non-zero-wait-state, direct access, write/read ? these two registers define the mac mask of ip multicast. ? default = h?ff:ff:ff:80:00:00?. 18.2.11.6 cfcbhdl - fcb handle register for cpu read ? access: non-zero-wait-stat e,direct access,read only ? address: h580 usage: when cpu requests a free fdb to write a frame, it must request a free fcb via this register. the register contains a free handle of fcb, which also pointer to a free fdb. ? cpu reads fcb handle: (when the cpu write fdb, it requires a fdb handle first). ? cpu checks cfcbhdl[31],h_rdy ready or not. if so , cpu gets the fcb hand le from cfcbhdl[9:0] 31 24 23 16 15 8 7 0 ipmcas0 mac 3 mac 2 mac 1 mac 0 ipmcas1 mac 5 mac 4 31 24 23 16 15 8 7 0 ipmcmsk0 mask 3 mask 2 mask 1 mask 0 ipmcmsk1 mask 5 mask 4
mds212 data sheet 94 zarlink semiconductor inc. bit [9:0] fcb_handle fcb handle address bit [30:10] reserved bit [31] h_rdy fcb handle ready 0=not ready 1=ready 18.2.11.7 cpu access internal rams (tables) usage: (refer to section 9.0 ?the high density instruction set computer (hisc)? on page 37 for details) ? the cpu uses the following methods to access the fi ve internal rams, including mcid, vlan port mapping (vmap), bm control table (bmct), fcb and transmission queue control (qcnt). ?registers: ? cpuircmd : command register ? cpuirdat0 : data register for specific entry of content bit[31:0] ? cpuirdat1 : data register for specific entry of content bit[63:32] ? cpuirdat2 : data register for specific entry of content bit[95 64] ? cpuirrdy : data read ready. ?cpu reads fcb ? cpu write the read command into cpuircmd with fcb handle, w/ r=0. and set c_rdy. also, set the table type = fcb, (cpuircmd[14]=1) ? frame engine puts the specified fcb content into cpuirdatl and cpuirdatm ? frame engine clear c_rdy ? frame engine set cpui rrdy[0] to notify cpu that the fcb data is ready to be read. ?cpu writes fcb ? cpu writes the content of fc b into cpuirdatl and cpuirdatm ? cpu writes the handle of fcb into cpuircmd [9:0], set cpuircmd [1 0] = 1,(write cmd), set cpuircmd[31]=1, cmd_rdy and set the table index to fcb, (cpuircmd[14]=1). ? frame engine clears cpuircmd [31], c_rdy, when frame engine reads fcb done ? apply the similar method to access the other four tables. 18.2.11.8 cpuircmd - cpu internal ram command register ? access: non-zero-wait-state, direct access,write/read ? address: h584 ? command for cpu accesses five internal tables bit [9:0] entry index the index of specified entry type = mcid(16) entry index[3:0] type = vmap(256) entry index[7:0] type = bmct(1k) entry index[9:0] type = fcb(1k) entry index[9:0] type = qcnt (64) entry index[5:0] bit [10] w/r write or read the table entry 0=read 1=write 31 30 10 9 0 h_rdy fcb_handle [11:0] 31 30 16 15 14 13 12 11 10 9 0 c_rdy qcnt fcb bmct vmap mcid w/r entry index [9:0]
mds212 data sheet 95 zarlink semiconductor inc. bit[15:11] table bit map bit maps of five tables. bit[11] mcid mcid=1 use mc id l table bit[12] vmap vmap=1 use vlan port mapping table (vmap) bit[13] bmct bmct=1 use buffer manager control table (bm control) bit[14] fcb fcb=1 use fcb table bit[15] qcnt qcnt=1 use transmission queue control table (qm control) bit [30:16] reserve bit [31] c_rdy command ready 0=not ready 1=ready 18.2.11.9 cpuirdat - cpu internal ram data register ? the 3 data registers are used when cpu reads or writes the content of the specified entry table. ? cpuirdat0 cpu internal ram da ta register for data[31:0] ? address: h588 ? cpuirdat1 cpu internal ram da ta register for data[63:32] ? address: h58c ? cpuirdat2 cpu internal ram da ta register for data[95:64] ? address: h590 ? access: non-zero-wait-state, direct access, write/read the content is dependent on the type of table, as described below: type = mc id (6bits) bit [5:0] mcid multicast id fifo data output (note that up to 16 for this version.) bit [31:6] reserved type = vmap table (27 bits) bit [11:0] vlan port enable [12:0] one bit for each ethernet mac port identify the ports associated with each vlan 0 = disable 1 = enable bit [12] reserved bit [24:13] vlan tag enable [12:0]one bit for each ethernet mac port 0 = disable 1 = enable 31 0 cpirdat0 data[31:0] cpirdat1 data[63:32] cpirdat2 data[95:64] 31 13 12 6 5 0 cpirdat0 mcid[5:0] 31 27 26 25 24 13 12 11 0 cpirdat0 re vlan tag enable [12:0] vlan port enable [12:0]
mds212 data sheet 96 zarlink semiconductor inc. bit [25] reserved bit [26] re remote ports enable: indi cate some members in the remote device. 0=disable 1=enable bit [31:27] reserved type = bmct (12bits) bit [11:0] bm buffer management control fifo output bm stores free fcb handles. (fcb handle=0 cannot be used.) bit [12:31] reserved type = fcb (56 bits) bit [55:0] fcb frame control block. refer to section 9.0 ?the high density instruction set computer (hisc)? on page 37 for detailed data structure. type = qcnt (79 bits) bit [2:0] que_s [2:0] queue size000=128 entries 001=128*2 entries 111=128*8=1k entries each entry contains 4 bytes bit [14:3] base [11:0]base poin ter to its transmission queue bit [25:15] ecnt [10:0]entry coun t: total entries in its queue. bit [35:26] wrpt [9 :0]write pointer address_write_entry[20:9]=base[11:0]+wrpt[9:7] address_write_entry[9:3]= wrpt[6:0] address_write_entry[2:0]= 0 (the address [2:0] is always equal to 0.) bit [45:36] rdpt [9:0]read pointer address_read_entry[20:9]=base[11:0]+rdpt[9:7] address_read_entry[9:3]= rdpt[6:0] address_read_entry[2:0]= 0 (the address [2:0] is always equal to 0.) bit[46] cv cache valid cv=1, cache of qu eue entry qe[31:0] is valid. bit[78:47] qe[31:0]cache a queue entry 31 12 11 0 cpuirdat 0 bm[11:0] 31 24 23 0 cpuirdat 0 fcb_data[31:0] cpuirdat 1 fcb_data[55:32] 31 26 25 15 14 4 3 2 0 cpuirdat0 wrpt[5:0] ecnt[10:0] base[11:0] qs[2:0] cpuirdat1 cache queue entry[16:0] cv rdpt[9:0] wrpt[9:6] cpuirdat2 cache queue entry[31:17]
mds212 data sheet 97 zarlink semiconductor inc. 18.2.11.10 cpuirrdy - internal ram read ready for cpu ? access: non-zero-wait-stat e, direct access, write/read ? address: h594 ? the frame engine sets this ready bit to notify the cpu that the requested data is ready to read. bit [0] r_rdy data in data registers is ready for cpu read bit [31:1] reserved 18.2.11.11 ledr - led register ? access: non-zero-wait-state, direct access, write/read ? address: h598 bit [7:0] udef1 user defined information status 1 for debug purpose bit [15:8] udef2 user defined information status 2 for debug purpose bit [23:16] udef3 user defined information status 3 for debug purpose bit [25:24] ht holding time for led signal (default=00) 00=8msec 01=16msec 10=32msec 11-64msec bit [27:26 lclk] led clock frequency (default=00) 00=100m/8=12.5mhz 01=100m/16=6.25mhz 10=100m/32=3.125mhz11=100m/64=1.5625mhz bit [30:28] reserve bit [31] ss start shift out the status bits out from the master device. this bit has no effect on slave chip. note: udef1-udef3 are used for debug purpose. the contents of udef1-3 are loaded by cpu and the usage of these are up to software. 18.2.12 ethernet mac port control registers ? one set for each ethernet mac port [11:0] 18.2.12.1 ecr0 - mac port control register ? access: non-zero-wait-state, direct access, write/read ? address: h0x0*4 x: port n (n=0 - 11) h000 ecr0_p0 h040 ecr0_p1 h080 ecr0_p2 h0c0 ecr0_p3 h100 ecr0_p4 h140 ecr0_p5 h180 ecr0_p6 31 1 0 rdy 31 30 28 27 26 25 24 23 16 15 8 7 0 ss lck ht udef3 udef2 udef1
mds212 data sheet 98 zarlink semiconductor inc. h1c0 ecr0_p7 h200 ecr0_p8 h240 ecr0_p9 h280 ecr0_p10 h2c0 ecr0_p11 bit [0] rr reset receiver bit [1] xr reset transmitter bit [2] re rx enable bit [31:3] reserved ? port is disabled when both rr & xr bits are set. 18.2.12.2 ecr1 - mac port configuration register ? access: non-zero-wait-state, direct access, write/read ? address: h0x1*4 x: port number h004 ecr1_p0 h044 ecr1_p1 h084 ecr1_p2 h0c4 ecr1_p3 h104 ecr1_p4 h144 ecr1_p5 h184 ecr1_p6 h1c4 ecr1_p7 h204 ecr1_p8 h244 ecr1_p9 h284 ecr1_p10 h2c4 ecr1_p11 configuration bits trunking port trunking id bits bit [0:2] tgid group id bit [3] te trunk enable 0= trunk disable 1= trunk enable unicast blocking control bits bit [5:4] block_uc_frame instruct s the rx mac to discard in coming unicast frames. this feature is used by spanning tree. 0x blocking, all frames (default state) 10 learning but not forwarding 11 forwarding all frames bit [6] ife ingress filter enable default = 0 31 32 1 0 re xr rr 31 24 23 17 16 15 8 7 6 5 4 3 2 0 ifg 10m ife bkuc te tg id
mds212 data sheet 99 zarlink semiconductor inc. used to enable protocol filtering on a port by port basis. there is only one protocol filtering register (pfr), but it can be used on any combination of ports. 0= disable ingress filter 1= enable ingress filter physical layer control bits bit [7] 10m 10m or 100m; 1=10mbps 0=100mbps bit [8] reserved bit [9] full_duplex enables full duplex mode default =0 ? half duplex bit [10] fdx_polarity selects the output polarity of full_duplex control signal 0 = low true (default) 1 = high true bit [11] int_lpback setting this bit cause internal connect txclk, txd, txd[0:3] to rxclk, rxd, rxd[0:3] default =0 ? disable bit [12] ext_lpback setting this bit indicate an external loop-back connection of txclk, txd[0:3] to rxclk, rxd[0:3] are required) default =0 -- disable bit [13] fc_enable flow control enable default =0 ? disable when enabled: ?in half duplex mode, the mac transmitter applies backpressure for flow control. ?in full duplex mode, the mac transmitter sends flow-control frames when necessary. the mac receiver interprets and processes incoming flow control fram es. the mac receiver marks all flow control frames. receive dma discards the received flow control frame and send status reports to the switch manager for statistic collection. when disabled: ? the mac transmitter asserts flow control neither by se nding flow control frames nor by jamming collision. ? the mac receiver still interprets and processes th e flow-control frames. the mac receiver marks all flow control frames. receive dma discards the received flow control frames and send a status report to the switch manager for statistic collection. bit [14] link_polarity selects the in put polarity of link status signal 0 = low true (default) 1 = high true bit [15] tx_enable enables mac transmitter for transmission default =0 ? disable bit [16] reserved bit [23:17] ifg inter-frame gap (default=7?d24) use to adjust the inter-frame g ap. (unit =transmit clock.) the default is 7'd24, stands for 24 transmit clock (each clock transmit 4 bits). bit [31:24] reserved 18.2.12.3 ecr2 - mac port interrupt mask register ? access: non-zero-wait-state, direct access, write/read ? address: h0x2*4 x: port number h008 ecr2_p0 h048 ecr2_p1 h088 ecr2_p2
mds212 data sheet 100 zarlink semiconductor inc. h0c8 ecr2_p3 h108 ecr2_p4 h148 ecr2_p5 h188 ecr2_p6 h1c8 ecr2_p7 h208 ecr2_p8 h248 ecr2_p9 h288 ecr2_p10 h2c8 ecr2_p11 bit [0] was if set, the status coun ter wrap around signal is masked. bit [1] link_change if set, the link_up and link_down interrupts are masked. bit [31:2] reserved ? link change interrupts are automatically disabled whenever both mac transmitter & receiver are in reset state ? i.e. both xr & rr bits are set. 18.2.12.4 ecr3 - mac port interrupt status register ? access: non-zero-wait-stat e, direct access, read only ? address: h0x3*4 x: port number h00c ecr3_p0 h04c ecr3_p1 h08c ecr3_p2 h0cc ecr3_p3 h10c ecr3_p4 h14c ecr3_p5 h18c ecr3_p6 h1cc ecr3_p7 h20c ecr3_p8 h24c ecr3_p9 h28c ecr3_p10 h2cc ecr3_p11 bit [0] was wrapped around signal. bit [1] link_change this bit is set when the mac determines that the status of physical link has been changed bit [2] lk_up 0=link down, 1=link up this bit is reset whenever the phy has identified the lost of physical link integrity. bit [31:3] reserved 31 2 1 ? 0 mask 31 32 1 0 status
mds212 data sheet 101 zarlink semiconductor inc. 18.2.12.5 ecr4 - port status counter wrapped signal ? access: non-zero-wait-stat e, direct access, read only ? address: h0x4*4 x: port number h010 ecr4_p0 h050 ecr4_p1 h090 ecr4_p2 h0d0 ecr4_p3 h110 ecr4_p4 h150 ecr4_p5 h190 ecr4_p6 h1d0 ecr4_p7 h210 ecr4_p8 h250 ecr4_p9 h290 ecr4_p10 h2d0 ecr4_p11 b[0]. 0-d bytes sent(d) b[1]. 1-l unicast frames sent b[2]. 1-u flow control sent b[3]. 2-l non-unicast frame sent b[4]. 2-u1 frame send fail b[5]. 2-u2 alignment error b[6]. 3-d bytes received (good or bad) (d) b[7]. 4-d frames received (good or bad) (d) b[8]. 5-d total bytes received (good) (d) b[9]. 6-l total frames received (good) b[10]. 6-u flow control frames received b[11]. 7-l multicast frames received b[12]. 7-u broadcast frames received b[13]. 8-l frames with length of 64 bytes b[14]. 8-u jabber frames b[15]. 9-l frames with length between 65-127 bytes b[16]. 9-u oversize frames b[17]. a-l frames with length between 128-255 bytes b[18]. a-u frames with length between 256-511 bytes b[19]. b-l frames with length between 512-1023 bytes b[20]. b-u frames with length between 1024-1528 bytes b[21]. c-l undersize frames b[22]. c-u fragment b[23]. d-l crc b[24]. d-u short event b[25]. e-l collision b[26]. e-u drop 31 30 26 25 0 status wrapped signal
mds212 data sheet 102 zarlink semiconductor inc. b[27]. f-l filtering counter b[28]. f-u1 delay exceed discard counter b[29]. f-u2 late collision note: each port owns a counter block, containing 16 double words. the 29 bits indicate that each corresponding counter is wrapping around the signal. the type and loca tion of each counter is specified by the following format. the format description: x-y: x means the relative physical address in its counter blocks. : y indicates the type of counter it is (notation ?c?= double word read from ram block) d: c[31:0] double word counter l: c[23:0] 24 bits counter u: c[31:24] 8 bits counter u1: c[23:16] 8 bits counter u2: c[31:24] bits counter (the same as notation ?u?) l: c[15:0] 16 bits counter u c[31:16] 16 bits counter 18.2.12.6 pvid register ? access: non-zero-wait-state, direct access, write/read ? address: h0x9*4 x: port number ? for default vlan id h024 pvidr_p0 h064 pvidr _p1 h0a4 pvidr _p2 h0e4 pvidr _p3 h124 pvidr _p4 h164 pvidr _p5 h1a4 pvidr _p6 h1e4 pvidr _p7 h224 pvidr _p8 h264 pvidr _p9 h2a4 pvidr _p10 h2e4 pvidr _p11 bit [0:11] port vlan id (pvid) bit [12] reserved bit [15:13] priority bit [31:16] reserved 31 24 23 16 15 13 12 11 8 7 0 priority port vlan id
mds212 data sheet 103 zarlink semiconductor inc. 19.0 dc electrical characteristics 19.1 absolute maximum ratings package: 456 hbga (heatslug bga) storage temperature: -65c to +150c operating temperature: 0c to +70c maximum junction temperature: 125c supply voltage vcc with resp ect to vss +3.0 v to +3.6 v supply voltage vdd with respect to vss +2.38 v to +2.75 v voltage on 5v tolerant input pins -0.5 v to (vcc + 3.3 v) caution: stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to the absolute maximum ratings for extended periods may affect device reliability. 19.2 dc electrical characteristics vcc = 3.0 v to 3.6 v (3.3v +/- 10%) t ambient = 0 c to +70 c vdd = 2.5v +10% - 5% note 1: when external heat sink is attached, ja is reduced by about 8-12% in still air. recommended operating conditions symbol parameter description min type max unit f osc frequency of operation 100 mhz i cc supply current ? @ 100 mhz (vcc =3.3 v) 220 286 ma i dd supply current ? @ 100 mhz (vdd =2.5 v) 720 936 v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) 0.8 v i il input leakage current (all pins except those with internal pull-up/pull-down resistors) 10 a i ol output leakage current 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 12 1 c/w ja thermal resistance with 1 m/s air flow 11 c/w ja thermal resistance with 2 m/s air flow 9.6 c/w jc thermal resistance between junction and case 3.3 c/w
mds212 data sheet 104 zarlink semiconductor inc. 20.0 ac specification 20.1 xpipe interface figure 24 - xpipe interface - output valid delay timing symbol parameter -100mhz note min (ns) max (ns) x1 x_dclko output valid delay 1 5 cl = 30pf x2 x_do[31:0] output valid delay 1 5 cl = 30pf x3 x_deno output valid delay 1 5 cl = 30pf x4 x_fco output valid delay 1 5 cl = 30pf x15 x_dclki input set-up time 3 reference s-clk x16 x_dclki input hold time 0 reference s-clk x17 x_di[31:0] input set-up time 3 x18 x_di[31:0] input hold time 0 x19 x_deni input set-up time 3 x20 x_deni input hold time 0 x21 x_fci input set-up time 3 x22 x_fci input hold time 0 table 14 - ac characteristics - xpipe interface x1-max x1-min x4-max x4-min x3-max x3-min x2-max x2-min x_dclk x_dclk x_fco x_deno x_do[31:0] x17 x19 x21 x23 x_dclk x_di[31:0] x_deni x_fci x18 x20 x22 x24 x15 x16 s_clk x_dclki
mds212 data sheet 105 zarlink semiconductor inc. 20.2 cpu bus interface figure 25 - cpu bus interface - output valid delay timing p19-max p19-min p23-max p23-min p24-max p24-min p_clk p_d[31:0] p_rdy# p_int p20-max p20-min p21-max p21-min p22-max p22-min p_a[10:1] p_rwc# p_ads# p25-max p25-min p26-max p26-min p_gntc p_gnt1
mds212 data sheet 106 zarlink semiconductor inc. figure 26 - cpu bus interface - input setup and hold timing symbol parameter -66mhz note min (ns) max (ns) p_clk p1 p_rst# input setup time 6 p2 p_rst# input hold time 2 p3 p_ads# input setup time 6 p4 p_ads# input hold time 2 p5 p_rwc# input setup time 6 p6 p_rwc# input hold time 2 p7 p_csi# input setup time 6 p8 p_csi# input hold time 2 p9 p_a[10:1] inpu t setup time 6 p10 p_a[10:1] input hold time 2 p11 p_d[31:0] input setup time 6 p12 p_d[31:0] input hold time 2 p15 p_reqc input setup time 6 p16 p_reqc input hold time 2 table 15 - ac characteristics - cpu bus interface p1 p_clk p_rst# p_ads# p_rwc# p_csi# p2 p 3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p_a[10:1] p_d[31:0] p15 p16 p17 p18 p_reqc p_req1
mds212 data sheet 107 zarlink semiconductor inc. 20.3 local sbram memory interface figure 27 - local memory interface - input setup and hold timing p17 p_req1 input setup time 6 p18 p_req1 input hold time 2 p19 p_d[31:0] output valid delay 2 12 cl = 65pf p20 p_a[10:1] output valid delay 2 9 cl = 50pf p21 p_rwc# output valid delay 2 9 cl = 50pf p22 p_ads# output va lid delay 2 9 cl = 50pf p23 p_rdy# output valid delay 2 9 cl = 50pf p24 p_int output valid delay 2 9 cl = 30pf p25 p_gntc output valid delay 2 9 cl =20pf p26 p_gnt1 output valid delay 2 9 cl =20pf symbol parameter -66mhz note min (ns) max (ns) table 15 - ac characteristics - cpu bus interface (continued) l_clk l_d[63:0] l2 l1
mds212 data sheet 108 zarlink semiconductor inc. figure 28 - local memory interface - output valid delay timing symbol parameter -100mhz notes min (ns) max (ns) l_clk c l =50pf l1 l_d[60:0] input set-up time 3 l2 l_d[63:0] input hold time 1.5 l3 l_d[63:0] output valid delay 2 7 c l =30pf l4 l_a[20:3] output valid delay 2 7 c l =50pf l6 l_adsc# output valid delay 2 7 c l =50pf l7 l_bw[7:0]# output valid delay 2 7 c l =30pf l8 l_we[1:0]# output valid delay 2 7 c l =30pf l9 l_oe[1:0]# output valid delay 0 1 c l =30pf table 16 - ac characteristics - local sbram memory interface l_ck l_d[63:0] l_a[20:3] l_adsc# l_bw[7:0]# l_we[1:0]# l_oe[1:0]# l3 max l3 min l4 max l4 min l6 max l6 min l7 max l7 min l8 max l8 min l9 max l9 min
mds212 data sheet 109 zarlink semiconductor inc. figure 29 - port mirroring interface - input setup and hold timing figure 30 - port mirroring interface - output delay timing figure 31 - reduce media independent interface - input setup and hold timing figure 32 - reduce media independent interface - output delay timing pm_deni m_clki pm_d[1:0] pm1 pm2 pm3 pm4 pm5 pm6-max pm6-min pm7-max pm7-min m_clki pm_deno pm_do[1:0] m[11:0]_rxd[1:0] m_clki m[11:0]_crs_dv m1 m2 m3 m4 m5 m6-max m6-min m7-max m7-min m_clki m[11:0]_txen m[11:0]_txd[1:0]
mds212 data sheet 110 zarlink semiconductor inc. figure 33 - led interface - output delay timing symbol parameter -50mz notes min (ns) max (ns) pm1 m_clk reference input clock pm2 pm_deni input setup time 1.5 pm3 pm_deni input hold time 2 pm4 pm_di[1:0] input setup time 1.5 pm5 pm_di[1:0] input hold time 2 pm6 pm_deno output delay time 2 11 cl = 30 pf pm7 pm_do[1:0] output delay time 2 11 cl = 30 pf table 17 - ac characteristics - port mirroring interface symbol parameter -50mz notes min (ns) max (ns) m1 m_clki reference input clock m2 m[11:0]_rxd[1:0] input setup time 1.5 m3 m[11:0]_rxd[1:0] input hold time 2 m4 m[11:0]_crs_dv input setup time 2 m5 m[11:0]_crs_dv input hold time 2 m6 m[11:0]_txen output delay time 2 11 cl = 30 pf m7 m[11:0]_txd[1:0] output delay time 2 11 cl = 30 pf table 18 - ac characteristics - reduced media independent interfac le2-max le2-min le3-max le3-min led_clko led_do led_synco le1
mds212 data sheet 111 zarlink semiconductor inc. symbol parameter variable freq. notes min (ns) max (ns) le1 le_di input le_clko times reference output clock le2 le_do output valid delay -1 7 cl = 30 pf le3 le_synco output valid delay -1 7 cl = 30 pf table 19 - ac characteristics - led interface
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: dimension conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 35.20 34.80 30.00 ref 456 1.27 0.60 0.90 30.00 ref 1.17 ref 34.80 min 0.50 2.20 35.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls are defined by the spherical crowns of the solder balls. 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 3. primary datum -c- and seating plane 5. not to scale. d e d1 e1 e a1 a a2
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